How to generate Verilog code from Deep Learning Network in MATLAB?
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I have trained a Deep Learning Network in MATLAb, now I have to genearte a Verilog code for the same. I went through Deep Learning HDL Toolbox, there I found the methods to deploy the network on FPGA but did not get any method to generate a Verilog code. Please help.
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Kiran Kintali
2021-6-15
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Deep Learning Processor Customization and IP Generation
Configure, build, and generate custom bitstreams and processor IP cores, estimate and benchmark custom deep learning processor performance
Deep Learning HDL Toolbox™ provides functions to configure, build, and generate custom bitstreams and a custom processor IP. Obtain performance and resource utilization of a pretrained series network on the custom processor. Optimize the custom processor by using the estimation results.
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Kiran Kintali
2021-6-15
Verilog option is available in the upcoming 21b pre-release as a dlhdl.ProcessorConfig processor config option.
Saurabh Kumar Yadav
2021-6-15
Kiran Kintali
2021-6-15
编辑：Kiran Kintali
2021-6-15
You need to follow these steps.
This example shows how to create a custom processor configuration and estimate the performance of a pretrained series network. You can then modify parameters of the custom processor configuration and re-estimate the performance. Once you have achieved your performance requirements you can generate a custom bitstream by using the custom processor configuration.
Currently VHDL is supported and Verilog generation support is available in a week or two with upcoming 21b pre-release.
Saurabh Kumar Yadav
2021-6-15
Kiran Kintali
2021-6-15
please reach out to support@mathworks.com and someone from the MathWorks team can walk you through the steps and show you how to use the feature.
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