Does HDL coder from Simulink support AXI-4 Stream Interface for Xilinx Zynq?

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owen chang
owen chang 2013-8-28
回答： Kiran Kintali 2021-5-24
Hi all, I have created an adder example and export to Xilinx Vivado 2013.2 using HDL coder, and integrated using Vivado IPI. this will allow user to wrte AXI-4 register offset 0x0,0x4 and LED on ZC702 Board will show the sum of 0x0,0x4 (free run mode).
this is the basic AXI-4 example.
and now i would like to explore more, and create example using AXI-4 Stream IP from Xilinx, but i don't know how to create a AXI-4 Stream compatible design block from Simulink/HDL coder? or i can only using standard AXI-4 interface?
ps.AXI-4 Stream interface is the best interface for signal and video process.
BR Owen

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Kiran Kintali
Kiran Kintali 2021-5-24
Getting Started with AXI4-Stream Interface in Zynq Workflow
This example uses:
View MATLAB Command
This example shows how to use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq hardware.
Before You Begin
To run this example, you must have the following software and hardware installed and set up:
To setup the Zedboard, refer to the Set up Zynq hardware and tools section in the example Getting Started with Targeting Xilinx Zynq Platform.Introduction
This example shows how to:
  1. Model a streaming algorithm using a simplified streaming protocol.
  2. Generate an HDL IP core with AXI4-Stream interface.
  3. Integrate the generated IP core into a Zedboard reference design with DMA controller.
  4. Use the AXI4-Stream driver block to generate C code that runs on an ARM processor.
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html

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