Problems in converting Matlab code to VERILOG (HDL Coder)
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Hi I have been trying to generate VERILOG code for Automotive Adaptive Cruise control model. I am converting matlab code into verilog code so that I can implement it on FPGA. But the conversion is not possible.
I have some error like this: "Expected R to be one of these types: double. Instead it is of type Embedded.fi"
I do not understand this error completely. Some one please help me out in solving this.
Regards
1 个评论
Kaustubha Govind
2013-9-20
Perhaps you can also post the snippet of code that the error points to.
回答(4 个)
Kiran Kintali
2013-9-20
0 个投票
Please contact technical support with the MATLAB code.
Most likely you are running into an operation or function which is not supported and needs to be replaced with a LUT or other approximation.
The error message seems to indicate variable 'R' cannot be fi type since it is not supported by Fixed-Point Designer.
Ravikanth
2013-9-21
0 个投票
3 个评论
Kaustubha Govind
2013-9-23
Ravikanth: What specific line(s) does the error occur at? Does the error message point to a specific part of the code?
Ravikanth
2013-9-24
Kaustubha Govind
2013-9-26
Is the type of the variable 'a' double or fi? I don't see that line in the file that you attached.
The message about parallelization seems to suggest that you are attempting to generate code from a PARFOR loop or some other Parallel Computing construct. Such parallelized code produces calls to OpenMP in generated code.
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