MATLAB function block doesn't generate synthesizable HDL.
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I developed an algorithm by using MATLAB function block and it responses properly. But, when I try to generate HDL code through HDL coder, then fail to do so with following errors.
"Signals of type double will not generate synthesizable HDL. For synthesizble code, consider enabling native floating point mode and retyping double typed signals to single".
Please help
采纳的回答
Kiran Kintali
2021-8-25
编辑：Kiran Kintali
2021-8-25
The issues you were facing are related to mix of incompatible single and double types in the model causing compilation issues in your model. See the updated model with very minor changes.
>> makehdl('EKFforHDLcoder190821/Subsystem')
### Generating HDL for 'EKFforHDLcoder190821/Subsystem'.
### Using the config set for model EKFforHDLcoder190821 for HDL code generation parameters.
### Running HDL checks on the model 'EKFforHDLcoder190821'.
### Begin compilation of the model 'EKFforHDLcoder190821'...
### Applying HDL optimizations on the model 'EKFforHDLcoder190821'...
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'EKFforHDLcoder190821'.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_div_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_div_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_add_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_add_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_sub_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_sub_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_mul_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_mul_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_sqrt_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_sqrt_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_atan_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_atan_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_exp_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_exp_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_gain_pow2_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_gain_pow2_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_uminus_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_uminus_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_recip_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_recip_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_pow_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_pow_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function as hdl_prj\hdlsrc\EKFforHDLcoder190821\MATLAB_Function.vhd.
### Working on EKFforHDLcoder190821/Subsystem as hdl_prj\hdlsrc\EKFforHDLcoder190821\Subsystem.vhd.
### Generating package file hdl_prj\hdlsrc\EKFforHDLcoder190821\Subsystem_pkg.vhd.
### Code Generation for 'EKFforHDLcoder190821' completed.
### Creating HDL Code Generation Check Report Subsystem_report.html
### HDL check for 'EKFforHDLcoder190821' complete with 0 errors, 1 warnings, and 0 messages.
### HDL code generation complete.
>>
The model genertes HDL code, but you would need to consider further pipelining and fixed-point conversion as necessary to improve generated HDL Code for improving ASIC/FPGA area efficiency and meeting timing/frequency/latency requirements.
Here are some useful links.
Hardware Modeling with MATLAB Code
Specifically look at Model State with Persistent Variables top here
I would highly recommend two day HDL Coder training on best modeling practices for FPGA/ASIC code generation.
Generating HDL Code from Simulink
Day 1 of 2
Preparing Simulink Models for HDL Code Generation
Objective: Prepare a Simulink model for HDL code generation. Generate HDL code and testbench for simple models requiring no optimization.
- Preparing Simulink models for HDL code generation
- Generating HDL code
- Generating a test bench
- Verifying generated HDL code with an HDL simulator
Fixed-Point Precision Control
Objective: Establish correspondence between generated HDL code and specific Simulink blocks in the model. Use Fixed-Point Tool to finalize fixed point architecture of the model.
- Fixed-point scaling and inheritance
- Fixed-Point Designer workflow
- Fixed-Point Tool
- Command-line interface
Generating HDL Code for Multirate Models
Objective: Generate HDL code for multirate designs.
- Preparing a multirate model for generating HDL code
- Generating HDL code with single or multiple clock pins
- Understanding and applying techniques used for clock domain crossing
Day 2 of 2
Optimizing Generated HDL Code
Objective: Use pipelines to meet design timing requirements. Use specific hardware implementations and share resources for area optimization.
- Generating HDL code with the HDL Workflow Advisor
- Meeting timing requirements via pipelining
- Choosing specific hardware implementations for compatible Simulink blocks
- Sharing FPGA/ASIC resources in subsystems
- Verifying that the optimized HDL code is bit-true cycle-accurate
- Mapping Simulink blocks to dedicated hardware resources on FPGA
Using Native Floating Point
Objective: Implement floating point values and operations in your HDL code.
- Why and when to use native floating point
- Target-independent HDL code generation with HDL Coder
- Fixed-point vs. floating point comparison
- Optimization of floating point implementations
Interfacing External HDL Code with Generated HDL
Objective: Incorporate hand-written HDL code and/or vendor party IP in your design.
- Interfacing external HDL code
Verifying HDL Code with Cosimulation
Objective: Verify your HDL code using an HDL simulator in the Simulink model.
- Verifying HDL code generated with HDL Coder
- Comparing manually written HDL code with a "golden model"
- Incorporating HDL code into Simulink for simulation
更多回答（5 个）
Bharath Venkataraman
2021-8-5
0 个投票
It appears that you have floating point values in your MATLAB code.
If you want to retain floating point numerics for your HDL, configure HDL Coder to generate floating point as shown in this page.
Another option is to convert these floating point variables to fixed point using the fi construct with signedness, wordlength and fraction length, and generate fixed-point HDL code.
Kiran Kintali
2021-8-6
0 个投票
Try the attached sample model which shows how to MATLAB function block with floating point single precision code using native floating point.
Kiran Kintali
2021-8-6
编辑：Kiran Kintali
2021-8-6
0 个投票
I am attaching R2018a version of the model for viewing the contents of the MATLAB function. I recommend upgrading to latest releases for HDL code generation. There are significant improvements in floating point code generation. Floating point code generation for MATLAB function block is available from 19b release.
https://www.mathworks.com/help/hdlcoder/release-notes.html
2 个评论
Khakoo Mal
2021-8-12
Walter Roberson
2021-8-12
"Floating point code generation for MATLAB function block is available from 19b release." implies to me that you need to upgrade to do what you want.
Kiran Kintali
2021-8-12
0 个投票
R2019b
New Features, Bug Fixes
Model and Architecture Design
HDL code generation for MATLAB Function block in native floating-point mode
In R2019b, HDL Coder™ supports code generation for the MATLAB Function block by using floating-point data types in Native Floating Point mode. You can use a wider subset of MATLAB® functions to develop complex floating-point algorithms.
By default, floating-point support in HDL Coder uses a new MATLAB datapath architecture of the MATLAB Function block. This architecture treats the MATLAB Function block like a Subsystem block. The generated HDL code with the MATLAB datapath architecture is more readable.
Kiran Kintali
2021-8-19
0 个投票
An operator or a block in Simulink can support all floating point types (for input, output and intermediate settings) that are set to same type (single, double, half). Check documentation on available floating point usage.
Consider using our automated tools to convert double to single or do manual conversion necessary to comply with supported usecases.
Please share your model for any further assistance.
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