Why are my the signal constraints specified by the Condition block not honored in Simulink Design Verifier 1.5 (R2009b)?

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MathWorks Support Team
I have a model in which I specify multiple sample times. I also have blocks in my model that execute at a slower rate than one of these Solver step times. This block may propagate its step time to the Input block as well. When I look at my inputs for my Model Verification, I see that the constraints I set on input values have been violated. Why is this?

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MathWorks Support Team
This is expected behavior in Simulink Design Verifier 1.5 (R2009b) in models with multiple sample times. The Condition block in Design Verifier inherit the sample time of the signals they are connected to and the signal constraints are only applied at the sample times of those signals.

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