HDL Verifier Support Package for Intel FPGA Boards

作者: MathWorks HDLVerifier Team
Debug and test HDL code on Intel FPGAs and SoC FPGAs
5.0
(2)
4.8K 次下载
更新时间 2024/4/3
HDL Verifier™ Support Package for Intel® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier and supported Intel FPGA and SoC FPGA boards. With FIL simulation, use MATLAB® or Simulink® to test designs in real hardware for any existing HDL code.
The FPGA Data Capture capability lets you observe signals from your design in MATLAB while the design is running on the Intel FPGA or SoC FPGA. Then use these signals in MATLAB or Simulink for analysis and verification, or view them using the Logic Analyzer in DSP System Toolbox.
AXI Manager IP included in the support package enables you to read from or write to on-board memory locations directly from MATLAB.
MATLAB 版本兼容性
创建方式 R2014a
兼容 R2014a 到 R2024a 的版本
平台兼容性
Windows macOS (Apple 芯片) macOS (Intel) Linux

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