Avnet RFSoC Explorer

版本 2.3.1 (90.4 MB) 作者: Avnet
Connect to Xilinx UltraScale+ RFSoC gigasample data converters. Perform analysis in MATLAB and Simulink. Deploy algorithms with HDL Coder.

2.0K 次下载

更新时间 2023/3/16


Connect to AMD RFSoC using MATLAB and Simulink
Avnet RFSoC Explorer® provides a visual interface to AMD Zynq® UltraScale+™ RFSoC using MATLAB and Simulink. An intuitive API enables programmatic control of all RF-ADC and RF-DAC parameters, signal generation, acquisition. System designers who want to test OTA signals can use Avnet RFSoC Explorer to control supported RF front-end cards for popular AMD RFSoC evaluation kits. Algorithm designers can generate IP cores for execution on RFSoC platforms.
Support and Documentation
Characterize RFSoC Performance
Development with AMD Zynq UltraScale+ RFSoC starts by characterizing the data converter subsystem using Avnet RFSoC Explorer. Avnet RFSoC Explorer enables you to use MATLAB and Simulink to stream standards-compliant 5G, LTE, and custom waveforms to and from hardware.
Avnet RFSoC Explorer System Diagram
Perform Over-the-Air Tests with RF Front-end Cards
Avnet RFSoC Explorer enables OTA testing by integrating control of RF front-ends connected to AMD Zynq UltraScale+ RFSoC Gen1 and Gen3 Evaluation Kits. Explore the entire signal chain in LTE 1800 MHz band-3 and mmWave bands between 19 and 31 GHz.
Supported platforms for RFSoC characterization and OTA test:
Write Test Scripts Easily with API and Auto-complete
Quickly write scripts that programmatically control of all RFSoC data converter parameters and RF add-on card signal chains. Auto-complete suggests commands and arguments to help you efficiently use the API.
Import Spreadsheet Presets for Automated Testing
Use the spreadsheet import capability (File > Open) to load sequenced presets into Avnet RFSoC Explorer and run comprehensive and repeatable test suites.
Deploy HDL Code for RFSoC
When you move into algorithm development, Avnet RFSoC Explorer Support for HDL Coder™ enables generation of IP cores that can integrate into RFSoC devices using AMD Vivado® Design Suite.
Avnet RFSoC Explorer HDL Coder Suppport for ZCU208
Supported platforms for HDL code generation:
With this support package you can generate HDL code and port mappings to I/O and AXI registers to build connections to RF tiles and DDR memory, and interactively control the FPGA design from MATLAB.


Avnet (2023). Avnet RFSoC Explorer (https://www.mathworks.com/matlabcentral/fileexchange/73665-avnet-rfsoc-explorer), MATLAB Central File Exchange. 检索来源 .

MATLAB 版本兼容性
创建方式 R2022b
兼容 R2022a 到 R2022b 的版本
Windows macOS Linux

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版本 已发布 发行说明

Bug fixes
Fixed API 'OpenFile' fixed
Reliable lock of CLK104 and downstream PLLs


Supports R2022a, R2022b
Enhanced DAC output plotting in IMR DUC modes for frequency planning
API cmd: Avnet_RFSoC_Explorer('getDtrx2Hw') reads settings from Otava DTRX2 card
API cmd: Avnet_RFSoC_Explorer('OpenFile') loads parameters from spreadsheet


Supported MATLAB versions: R2022a, R2021b
Import settings from spreadsheet using File > Open
API cmd: Avnet_RFSoC_Explorer('ADC_setDSA')
API cmd: Avnet_RFSoC_Explorer('DAC_setVOP')
Auto-complete when typing API commands
Run app from any directory


Support for two most recent MATLAB versions: R2021a, R2021b.
Save ADC data for multiple channels & multiple captures.
New API cmds.
Multiple bug fixes, including issue with duplicate/shadowed paths.


Fixes an error reported, related to a missing graphics file.


API programmatic control of all RF-ADC and RF-DAC parameters, signal generation, acquisition
Support for Xilinx RFSoC Gen3 on the Xilinx ZCU208 platform
Support for Avnet Wideband mmWave Radio Development Kit for RFSoC Gen-3
Multiple bug fixes


Minor release v1.1.0 adds 2 features:
- Enables global programming of DAC output current
- Copies ADC sample buffer to base workspace


Added link to free MATLAB Wireless trial package and acknowledgment to Communications Toolbox™ Support Package for Xilinx® Zynq®-Based Radio


Minor typographical corrections


Revised description and project website URL.