Igor Freire

Universidade Federal do Pará

Last seen: 17 days 前 | 自 2017 起处于活动状态

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统计学

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Fpga-in-the-loop using IP core generation workflow with reference design?
Hi, Thanks for the information. These alternatives may be helpful at some point. However, I think the use that I was envision...

7 years 前 | 0

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Fpga-in-the-loop using IP core generation workflow with reference design?
Hi, I would like to generate a baseband processor IP using HDL coder and implement it on an FPGA connected to Simulink (in th...

7 years 前 | 2 个回答 | 0

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