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zhang zheng


ustc

Last seen: 12 days 前 |  自 2020 起处于活动状态

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统计学

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Can I generate HDL Code for models with Xilinx System Generator blocks?
i come across the similar problem, and i've asked it on xilinx's forum, but until now get no answer. https://forums.xilinx.com/...

4 years 前 | 0

已回答
FFT Error on FPGA with FPGA in the Loop workflow
i've tested the simulink model you attached. i think maybe you attached the wrong model? in the attached model, 1. you combin...

4 years 前 | 0

已回答
[Fixed Point Converter] 1000 bit fraction length at 2^x if x is loaded from .mat file?
i also sometimes find fixedpoint-tool is not easy to understand. i often first convert m-code from float point to fixed point, a...

4 years 前 | 0