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face this error when wanna generate HDL coder "The Block/HDLImplementation pair: ('built-in/Reference', 'Module') is not registered in the implementation database."
Please reach out to support@mathworks.com This seems to be some sort of installation issue.

3 years 前 | 0

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PWM IP core FPGA
You can use core Simulink blocks to build a waveform of your choice.

3 years 前 | 0

| 已接受

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HDL QAM Transmitter and Receiver simulation problem
Please reach out to tech support for further support on this question. Thanks

3 years 前 | 0

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Pipelining using HDL Coder
Can you share some sample code and the project file? if the critical path is within optimized IP such as hdl.FFT distributed pi...

3 years 前 | 0

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How to solve Algebric loop error without adding delay.
HDL Coder supports various memory interfaces including AXI4 and DDR memory access. https://www.mathworks.com/help/hdlcoder/ug/p...

3 years 前 | 0

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How to use signed bitconcat and bitsliceget?
The bitwise operator functions such as bitsliceget and bitconcat operate on underlying stored integer bits. Once bitwise operat...

3 years 前 | 0

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Problem in generating reusable Verilog code using Simulink HDL Coder
Feel free to reach out to technical support for this question. You may want to try to use the new subsystem reuse algorithm ava...

4 years 前 | 0

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Fast compilation Simulink Model : Recommeded Configuration of PC
It would be best to reach out to MathWorks support on this question.

4 years 前 | 0

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Usage of HDL and HLS blocks in same SystemGenerator for DSP design
can you share your model? Are you looking for a solution similar to this? https://www.mathworks.com/help/hdlcoder/ug/using-xil...

4 years 前 | 0

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How to serialize an HDL Coder function with a vector input ?
Can you share you algorithm? You would need to share a design.m and a testbech.m files. Thanks

4 years 前 | 0

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fixed point taylor sine/cosine approximation model
HDL Coder supports code generation for single precision trigonometric functions. Getting Started with HDL Coder Native Floatin...

4 years 前 | 0

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Which versions of Xilinx Vivado are supported with which release of HDL Workflow Advisor?
https://www.mathworks.com/help/hdlcoder/supported-hardware.html The supported official versions of Simulation and Synthesis too...

4 years 前 | 0

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Bitstream generation problem in HDL coder
Is it possible to attach a sample model? Feel free to reach out to MathWorks technical support on this question.

4 years 前 | 0

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up sample Simulink doesn't implement rate convertion on hdl coder
Please share your model. I do not see any such errors with a basic model with your sample settings.

4 years 前 | 0

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Can HDL coder produce code for unit delay with initial condition input
This feature is not currently supported and is on the future HDL Coder roadmap. For the block 'model/DUTSubsystem/Delay' ...

4 years 前 | 0

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PMSM is programed in FPGA using HDL coder.
In the motor control demo project the current control algorithm and speed control runs on FPGA and processor respectively and th...

4 years 前 | 0

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PMSM is programed in FPGA using HDL coder.
I think you are referring to this example. https://www.mathworks.com/videos/deploy-motor-control-algorithms-to-fpga-hardware-pro...

4 years 前 | 0

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Modeling S-R Flip flip for HDL code generation
Attached in an example model that works in 22a release.

4 years 前 | 0

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The top design unit selected for HDL code generation may not be inside a triggered subsystem.
The DUT targeted for code generation can be a whole model with root ports, or a regular virtual or atomic subystem, model refere...

4 years 前 | 0

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makehdltb. Dont open generated model.
I am assuming the act of simulation of your model opens scopes; HDL Coder simulates the model to collect stimulus and response o...

4 years 前 | 0

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What does 'coder.internal.indexShapeCheck>>errORWarnIF .... code generation assumption about size violated' mean?
This error is unexpected. Please share a sample project file that reproduces the error or reach out to technical support. HDL Co...

4 years 前 | 0

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How set block parameter over Zynq AXIS Lite bus?
https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-parameters.html Generate DUT Ports for Tunable Paramet...

4 years 前 | 1

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Zynq workflow error in step 4.2
This is an unepxected error issue. Please contact tech support for a solution and the next steps.

4 years 前 | 0

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how to solve this error?
Results from FPGA synthesis tool cannot be backannotated to model if they fall within Stateflow Block. This is a known limitatio...

4 years 前 | 0

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How to get list of all optimizations requested by subsystems in HDL Coder model?
>> hdlsaveparams('<path_to_the_dut>') >> help hdlsaveparams % PARAMETERSET = hdlsaveparams(DUT, FILENAME, FORCE_OVERWRITE)...

4 years 前 | 0

| 已接受

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Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t
This is an unexpected error. Can you reach out MathWorks support team with the reproduction steps for a resolution and a worka...

4 years 前 | 1

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HDL coder error (Invalid feature 'ModelAdvisorGenerateNewStyleViewSwitchInGUI)
We are unable to reproduce this issue. Please contact local technical support for additional guidance.

4 years 前 | 0

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Workflow advisor synthesis error
Can you attach a sample project and design files to reproduce this error?

4 years 前 | 0

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Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...

4 years 前 | 0

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Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...

4 years 前 | 0