Hardware Implementation of High-Performance FFT Algorithms on FPGAs

DSP algorithms are challenging to implement on hardware, and hardware design engineers have little to no opportunity for design exploration. DSP HDL Toolbox™ helps engineers make design decisions early in the development cycle using pre-verified, hardware-ready Simulink^® blocks that simulate hardware implementation of the algorithm. Using the fast Fourier transform block, learn:

• How to quickly change implementation options for low resource usage and latency designs
• How to change incoming streaming data from sample- to frame-based processing
• How to generate readable and synthesizable VHDL or Verilog using HDL Coder capabilities