ASIC Testbench for HDL Verifier

ASIC Testbench for HDL Verifier

Generate testbenches for ASIC and advanced FPGA designs

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ASIC Testbench for HDL Verifier is an add-on that enables HDL Verifier to generate test components and verification models from MATLAB or Simulink into Universal Verification Methodology (UVM) or SystemVerilog environments. These models run natively in HDL simulators such as Siemens® Questa™, Cadence® Xcelium™, Synopsys® VCS®, and AMD® Vivado® via the SystemVerilog Direct Programming Interface (DPI).

  • Generate DPI components from MATLAB and Simulink.
  • Create UVM components or environments from MATLAB and Simulink.
  • Export SystemC™ TLM-compatible transaction-level models from Simulink. 
ASIC Testbench Overview

What Is ASIC Testbench?

Illustration showing SystemVerilog testbench generation.

Produce SystemVerilog DPI

Generate SystemVerilog DPI components from MATLAB functions or Simulink subsystems for use in functional verification environments including Synopsys VCS, Cadence Xcelium, Siemens ModelSim™ or Questa, and the AMD Vivado Simulator.

Illustration showing Universal Verification Methodology testbench generation.

Generate UVM Environments

Export UVM verification components or complete verification environments from Simulink to Questa, Xcelium, and VCS simulators. Generate UVM sequences, scoreboards, and predictors, and then incorporate them into production testbenches.

Diagram showing generation of a TLM component, a TLM component testbench, and test vectors from a Simulink model.

Generate SystemC TLM 2.0 Compatible Transaction-Level Models

Build SystemC virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations. Use the TLM generator to produce IP-XACT files with mapping information between Simulink and generated TLM components.

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