本页面提供的是上一版软件的文档。当前版本中已删除对应的英文页面。

自定义板和参考设计

R2026a

通过定义自定义板和参考设计将生成的 IP 核集成到目标 SoC 器件中

HDL Coder™ 可以生成可部署到 Xilinx^® Zynq^® 平台上的 IP 核。您可以将生成的 IP 核集成到默认系统参考设计中，或集成到可以为板注册的自定义参考设计中。

类

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design
`hdlcoder.sdr`

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor

`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addAXI4SlaveInterface`	Add and define register interface using AXI4 and AXI4-Lite protocol
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface
`addFPGADataCaptureInterface`	Add and define FPGA Data Capture interface (自 R2025a 起)

`addCustomEDKDesign`	指定 Xilinx EDK MHS 工程文件
`addCustomVivadoDesign`	指定 Xilinx Vivado 导出的模块设计 Tcl 文件
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	检查参考设计对象中的属性值
`validateBoard`	检查板卡对象中的属性值

`CallbackCustomProgrammingMethod`	Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
`EmbeddedCoderSupportPackage`	Specify whether to use an Embedded Coder support package
`PostBuildBitstreamFcn`	Function handle for callback function that gets executed after the build FPGA bitstream task runs
`PostCreateProjectFcn`	Function handle for callback function that gets executed after the create project task runs
`PostSWInterfaceFcn`	Function handle for custom callback function that gets executed after the generate software interface task runs
`PostTargetInterfaceFcn`	Function handle for callback function that gets executed after the set target interface task runs
`PostTargetReferenceDesignFcn`	Function handle for callback function that gets executed after the target reference design is set

Board and Reference Design Registration System
System for defining and registering boards and reference designs.
注册自定义板卡
定义自定义 SoC 板的接口和属性。在定义板卡后，您可以使用 HDL 工作流顾问中的 IP 核生成工作流将其作为目标。
Register a Custom Reference Design
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Define Custom Parameters and Callback Functions for Custom Reference Design
Learn how to define custom parameters and custom callback functions for your custom reference design.
Define and Add IP Repository to Custom Reference Design
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.