FPGA 数据采集
使用 Xilinx® Zynq® UltraScale+™ ZCU111 评估工具包或 Xilinx Zynq UltraScale+ ZCU216 评估工具包的 FPGA 输入和输出 (IO) 应用程序编程接口 (API) 采集原始数据。使用 HDL 工作流顾问为 HDL 代码生成配置 SoC 模型。为算法生成 HDL 代码，构建 HDL 设计并将其部署在 RFSoC 器件上，运行 MATLAB® 脚本以交互方式从部署的 HDL 设计采集数据。
工具
| Zynq RFSoC 模板构建器 | Generate template model based on selected RFSoC reference design (自 R2021a 起) |
主题
- Create RFSoC HDL Coder Models
This workflow customizes and designs an RFSoC model using the Zynq RFSoC Template Builder tool.
- ARM Targeting
Design and deploy algorithms to the ARM® processor.
精选示例
DAC and ADC Data Loopback on RFSoC Device
Capture raw analog-to-digital converter (ADC) data using the FPGA I/O API from the AMD® Zynq® UltraScale+(TM) ZCU111 or ZCU216 evaluation kit. This example uses the HDL Workflow Advisor to configure an SoC model for HDL code generation. In this example, you generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.
RF Data Converter IQ Mixer Mode on RFSoC Device
Enable the RFSoC built-in numerically-controlled oscillator (NCO) mixer. The mixer design uses a different data format that, instead of providing real signals, provides a complex in-phase and quadrature (IQ) signal to a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). There is more data to transfer to direct memory access (DMA) and back to MATLAB® given that you need to transfer I and Q samples back. You can accommodate this larger data width by increasing the DMA data width to 128 bits.
