FPGA Data Capture

Capture data to MATLAB or Simulink from RFSoC devices

Capture raw data using FPGA input and output (IO) application programming interface (API) from the Xilinx^® Zynq^® UltraScale+™ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit. Configure an SoC model for the HDL code generation by using the HDL Workflow Advisor. Generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB^® script to interactively capture data from the deployed HDL design.

Tools

Zynq RFSoC Template Builder

Generate template model based on selected RFSoC reference design (Since R2021a)

Topics

Create RFSoC HDL Coder Models
This workflow customizes and designs an RFSoC model using the Zynq RFSoC Template Builder tool.
ARM Targeting
Design and deploy algorithms to the ARM^® processor.
DAC and ADC Data Loopback
Capture raw analog-to-digital converter (ADC) data using the FPGA I/O API from the AMD Zynq® UltraScale+(TM) evaluation kit
RF Data Converter IQ Mixer Mode
Enable the RFSoC built-in numerically-controlled oscillator (NCO) mixer.