关键路径估计
R2026b关键路径是输入和输出之间具有最大时序延迟的组合路径。要快速确定设计中最可能的关键路径，请使用关键路径估计。关键路径估计加速寻找关键路径的此迭代过程。它优化关键路径，直到您的设计时序满足所需的目标频率。
函数
genhdltdb | Generate timing databases for specified target device, device speed grade, and synthesis tool |
模型设置
| 基于使能的约束 | Enable multiple clock cycles for data to propagate between registers |
| 生成高级时序关键路径报告 | Insert highlighting script that maps estimated critical path in code generation report |
| 自定义时序数据库目录 | Path to custom timing files |
类
hdlcoder.TimingGenerator | Base class to implement custom tool and device support for critical path estimation reporting (自 R2024a 起) |
主题
- Critical Path Estimation Without Running Synthesis
Find the estimated critical paths in your design without using third-party synthesis tools.
- Enable-Based Multicycle Path Constraints
Generate enable-based constraints for synthesis tools to meet timing requirements of multicycle paths in single clock mode.
- Generate Custom Timing Database for Custom Tools and Devices
Create a custom timing generator to characterize custom devices for your custom tools.
- Distributed Pipelining Using Synthesis Timing Estimates
Use synthesis timing estimates for distributed pipelining to more accurately reflect how components function on hardware to better distribute pipelines and increase clock frequency for your target device.
- Generate Multicycle Path Constraints for Multirate Models
Generate Multicycle Path Constraints for Different Rates and Phases.
- Choose Between Multicycle Path Constraints and Clock-Rate Pipelining
Decide whether to use multicycle path constraints (MCP) or clock-rate pipelining (CRP) to meet timing requirement.
精选示例
Use Multicycle Path Constraints to Meet Timing for Slow Paths
Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see Enable-Based Multicycle Path Constraints.
Iteratively Meet Timing Requirements Using Multicycle Path Constraints for Cadence Genus
Use multicycle path constraints with HDL Workflow Advisor and Cadence® Genus synthesis tools to meet the timing requirements for ASIC devices.
