外部存储访问
HDL Coder™ 参考设计提供了一种方法，可通过使用 AXI4-Master 将 IP 设计连接到可编程逻辑 (PL) 双倍数据速率 4 (DDR4) 内存接口。从 PL-DDR4 内存采集模数转换器 (ADC) 数据，并将从 PL-DDR4 内存中读取的波形从数模转换器 (DAC) 发射出去。
精选示例
ADC Data Capture to DDR Memory on RFSoC Device
Perform analog-to-digital converter (ADC) data captures with programmable logic (PL) double data rate 4 (DDR4) memory.
DAC Data Transmit from DDR Memory on RFSoC Device
Transmit waveforms out of the digital-to-analog converter (DAC) that is read from programmable logic (PL) double data rate 4 (DDR4) memory. Using PL-DDR4 memory offers advantages such as the ability to access 4 gigabytes of memory space. This amount of memory can help facilitate applications requiring large waveform transmissions that are not normally feasible with FPGA block random access memory (BRAM). This figure shows the relevant intellectual property (IP) interfaces and connectivity that are used in this design.
