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Generate SystemVerilog Code for a Simulink Model

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This example shows how to generate SystemVerilog HDL code from a Simulink® model. SystemVerilog code has more advanced features over that Verilog® code, such as the use of array ports, package declarations, structure ports and more.

Open the Model

Open the SystemVerilogFromSimulink model. The model adds two vector inputs of type uint8 and outputs the result.

mdl = 'SystemVerilogFromSimulink';
dut = [mdl '/HDL_DUT'];
open_system(mdl);

Generate SystemVerilog Code in Simulink

To generate SystemVerilog code:

  1. In the Modeling tab of the Simulink® toolstrip, click Model Settings to open the Configuration Parameters dialog box.

  2. In the HDL Code Generation pane, set Language to SystemVerilog. Click OK

  3. In Simulink®, in the Apps tab, click HDL Coder.

  4. Select the subsystem for which you want to generate the SystemVerilog code. For the SystemVerilogFromSimulink model, in the HDL Code tab, set the Code For parameter to HDL_DUT.

  5. Generate SystemVerilog code for the HDL_DUT subsystem by clicking Generate HDL Code.

Generate SystemVerilog Code from the MATLAB Command Window

You can also generate SystemVerilog code for your design under test (DUT) by using makehdl function. Run these commands in the MATLAB® Command Window to generate code for HDL_DUT subsystem.

load_system(mdl);
hdlset_param(mdl, 'TargetLanguage', 'SystemVerilog');
makehdl(dut)

### Working on the model <a href="matlab:open_system('SystemVerilogFromSimulink')">SystemVerilogFromSimulink</a>
### Generating HDL for <a href="matlab:open_system('SystemVerilogFromSimulink/HDL_DUT')">SystemVerilogFromSimulink/HDL_DUT</a>
### Using the config set for model <a href="matlab:configset.showParameterGroup('SystemVerilogFromSimulink', { 'HDL Code Generation' } )">SystemVerilogFromSimulink</a> for HDL code generation parameters.
### Running HDL checks on the model 'SystemVerilogFromSimulink'.
### Begin compilation of the model 'SystemVerilogFromSimulink'...
### Working on the model 'SystemVerilogFromSimulink'...
### Working on... <a href="matlab:configset.internal.open('SystemVerilogFromSimulink', 'GenerateModel')">GenerateModel</a>
### Begin model generation 'gm_SystemVerilogFromSimulink'...
### Copying DUT to the generated model....
### Model generation complete.
### Generated model saved at <a href="matlab:open_system('hdlsrc/SystemVerilogFromSimulink/gm_SystemVerilogFromSimulink.slx')">hdlsrc/SystemVerilogFromSimulink/gm_SystemVerilogFromSimulink.slx</a>
### Begin SystemVerilog Code Generation for 'SystemVerilogFromSimulink'.
### Working on SystemVerilogFromSimulink/HDL_DUT as hdlsrc/SystemVerilogFromSimulink/HDL_DUT.sv.
### Generating package file hdlsrc/SystemVerilogFromSimulink/HDL_DUT_pkg.sv.
### Code Generation for 'SystemVerilogFromSimulink' completed.
### Generating HTML files for code generation report at <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc24b_2725827_3887152/tpc6f3816c/hdlcoder-ex97853341/hdlsrc/SystemVerilogFromSimulink/html/SystemVerilogFromSimulink_codegen_rpt.html')">SystemVerilogFromSimulink_codegen_rpt.html</a>
### Creating HDL Code Generation Check Report file:///tmp/Bdoc24b_2725827_3887152/tpc6f3816c/hdlcoder-ex97853341/hdlsrc/SystemVerilogFromSimulink/HDL_DUT_report.html
### HDL check for 'SystemVerilogFromSimulink' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

After the HDL code generation completes, open the generated SystemVerilog files to examine the generated code for your DUT. The generated SystemVerilog code has vector port declaration for the DUT interfaces. HDL Coder also generates a package file for the typedef declarations of the DUT ports.

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