coder.HlsConfig

R2026b

HLS code generation configuration object configuration object

Since R2026b

Description

A coder.HlsConfig object contains the configuration parameters that the codegen function requires to generate High-Level Synthesis (HLS) code from MATLAB^® code. To pass this object to the codegen function, use the -config option.

Creation

Syntax

hlscfg =
coder.config("hls")

Description

hlscfg = coder.config("hls") creates a coder.HlsConfig object for HLS code generation.

example

Properties

expand all

Report

`GenerateCodeReplacementReport` — Option to generate a code replacement report
`false` or `0` (default) | `true` or `1`

Option to generate a code replacement report, specified as a numeric or logical 1 (true) or 0 (false). When true, generates a report showing which functions and operators were replaced by entries from the code replacement library.

Data Types: logical

`GenerateReport` — Option to generate code generation report
`false` or `0` (default) | `true` or `1`

Option to generate an HLS code generation report, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`LaunchReport` — Option to open code generation report
`false` or `0` (default) | `true` or `1`

Option to open the code generation report after code generation completes, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`ReportInfoVarName` — Name of variable to store report information
`''` (default) | `"variable name"`

Name of the variable in the base workspace to store code generation report information, specified as a character vector or string scalar.

Data Types: char | string

Comments

`GenerateComments` — Option to include comments in generated code
`true` or `1` (default) | `false` or `0`

Option to include comments in the generated HLS code, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`MATLABSourceComments` — Option to include MATLAB source code as comments
`false` or `0` (default) | `true` or `1`

Option to include MATLAB source code as comments in the generated HLS code, specified as a numeric or logical 1 (true) or 0 (false). When true, each line of generated code is preceded by the corresponding MATLAB source code as a comment.

Data Types: logical

General

`DesignFunctionName` — Name of the design function
`''` (default) | `"function name"`

Name of the design function for HLS code generation, specified as a character vector or string scalar.

Data Types: char | string

`EnableTraceability` — Option to enable traceability between MATLAB code and generated HLS code
`true` or `1` (default) | `false` or `0`

Option to enable traceability between MATLAB source code and generated HLS code in the code generation report, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`GenerateResourceReport` — Option to generate a resource utilization report
`true` or `1` (default) | `false` or `0`

Option to generate a resource utilization report, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`TargetLanguage` — Target language of the generated code
`"SystemC"` (default)

Target language of the generated HLS code, specified as a character vector or string scalar.

Data Types: char | string

`TestBenchName` — Test bench function name
`''` (default) | `"test bench name"`

Test bench function name, specified as a character vector or string scalar. The test bench function exercises the design function with representative input data. Specify a test bench to enable HLS test bench generation and verification.

Data Types: char | string

`Workflow` — HLS code generation workflow
`"Generic ASIC/FPGA"` (default)

HLS code generation workflow, specified as a character vector or string scalar.

Data Types: char | string

Workflow

`CheckConformance` — Option to check design conformance
`false` or `0` (default) | `true` or `1`

Option to check design conformance before generating HLS code, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`GenerateHLSCode` — Option to generate HLS code
`true` or `1` (default) | `false` or `0`

Option to generate HLS code, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`GenerateHLSTestBench` — Option to generate an HLS test bench
`false` or `0` (default) | `true` or `1`

Option to generate an HLS test bench, specified as a numeric or logical 1 (true) or 0 (false). When true, generates a test bench that verifies the generated HLS code against the MATLAB design.

Data Types: logical

`HLSTestBenchStimulus` — HLS test bench stimulus source
`"HLS Test bench stimulus"` (default)

HLS test bench stimulus source, specified as a character vector or string scalar.

Data Types: char | string

`LaunchConformanceReport` — Option to open the conformance report
`false` or `0` (default) | `true` or `1`

Option to open the conformance report after the conformance check completes, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`SimulateGeneratedCode` — Option to simulate generated code
`false` or `0` (default) | `true` or `1`

Option to simulate the generated HLS code by using the synthesis tool, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`SynthesizeGeneratedCode` — Option to synthesize generated code
`false` or `0` (default) | `true` or `1`

Option to synthesize the generated HLS code by using the synthesis tool, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

IP Core Options

`BitstreamBuildMode` — Bitstream build mode
`"Internal"` (default)

Bitstream build mode, specified as a character vector or string scalar.

Data Types: char | string

`BuildBitstream` — Option to build bitstream
`false` or `0` (default) | `true` or `1`

Option to build the FPGA bitstream after synthesis, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`CreateEmbeddedSystemProject` — Option to create an embedded system project
`false` or `0` (default) | `true` or `1`

Option to create an embedded system project, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`EmbeddedSystemTool` — Embedded system tool
`"Xilinx PlanAhead with Embedded Design"` (default)

Embedded system tool name, specified as a character vector or string scalar.

Data Types: char | string

`ExecutionMode` — IP core execution mode
`"Free running"` (default)

IP core execution mode, specified as a character vector or string scalar.

Data Types: char | string

`GenerateHostInterfaceScript` — Option to generate a host interface script
`false` or `0` (default) | `true` or `1`

Option to generate a host interface script, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`IPAddress` — IP address of target device
`"192.168.1.101"` (default)

IP address of the target device, specified as a character vector or string scalar.

Data Types: char | string

`IPCoreName` — IP core name
`''` (default) | `"IP core name"`

IP core name, specified as a character vector or string scalar.

Data Types: char | string

`IPCoreVendorName` — IP core vendor name
`''` (default) | `"vendor name"`

IP core vendor name, specified as a character vector or string scalar.

Data Types: char | string

`IPCoreVersion` — IP core version
`''` (default) | `"version"`

IP core version, specified as a character vector or string scalar.

Data Types: char | string

`ProgramTargetDevice` — Option to program the target device
`false` or `0` (default) | `true` or `1`

Option to program the target device with the generated bitstream, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`ProgrammingMethod` — Programming method for the target device
`"Download"` (default)

Programming method for the target device, specified as a character vector or string scalar.

Data Types: char | string

`ReferenceDesign` — Reference design name
`''` (default) | `"reference design name"`

Reference design name, specified as a character vector or string scalar.

Data Types: char | string

`ReferenceDesignPath` — Path to the reference design
`''` (default) | `"path"`

Path to the reference design folder, specified as a character vector or string scalar.

Data Types: char | string

`SSHPassword` — SSH password for target device
`"root"` (default)

SSH password for connecting to the target device, specified as a character vector or string scalar.

Data Types: char | string

`SSHUsername` — SSH username for target device
`"root"` (default)

SSH username for connecting to the target device, specified as a character vector or string scalar.

Data Types: char | string

`TargetPlatform` — Target platform name
`''` (default) | `"platform name"`

Target platform name for IP core generation, specified as a character vector or string scalar.

Data Types: char | string

Target Tool Selection

`SynthesisTool` — Synthesis tool name
`''` (default) | `"AMD Vitis HLS"` | `"Cadence Stratus HLS"`

HLS synthesis tool name, specified as a character vector or string scalar.

Example: "AMD Vitis HLS" "Cadence Stratus HLS"

Data Types: char | string

`SynthesisToolChipFamily` — Synthesis target chip family name
`''` (default) | `"family name"`

Synthesis target chip family name, specified as a character vector or string scalar.

Data Types: char | string

`SynthesisToolDeviceName` — Synthesis target device name
`''` (default) | `"device name"`

Synthesis target device name, specified as a character vector or string scalar.

Data Types: char | string

`SynthesisToolPackageName` — Synthesis target package name
`''` (default) | `"package name"`

Synthesis target package name, specified as a character vector or string scalar.

Data Types: char | string

`SynthesisToolSpeedValue` — Synthesis target speed value
`''` (default) | `"speed value"`

Synthesis target speed value, specified as a character vector or string scalar.

Data Types: char | string

`TargetFrequency` — Target clock frequency in MHz
0 (default)

Target clock frequency in MHz, specified as a nonnegative scalar. Specify the target frequency of the clock for HLS synthesis. A value of 0 uses the default frequency of the synthesis tool.

Data Types: double

Code Style

`ComplexImagPostfix` — Postfix for imaginary part of complex signals
`"_im"` (default) | `"postfix"`

Postfix string appended to signal names to form the imaginary part of complex signals, specified as a character vector or string scalar.

Data Types: char | string

`ComplexRealPostfix` — Postfix for real part of complex signals
`"_re"` (default) | `"postfix"`

Postfix string appended to signal names to form the real part of complex signals, specified as a character vector or string scalar.

Data Types: char | string

`DateComment` — Option to include date and time in generated file header
`true` or `1` (default) | `false` or `0`

Option to include the date and time in the generated file header, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`GenerateHLSCodeRegions` — Option to generate HLS code regions
`false` or `0` (default) | `true` or `1`

Option to generate HLS code regions in the generated code, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`InitializeBlockRAM` — Option to initialize block RAM
`true` or `1` (default) | `false` or `0`

Option to initialize block RAM to 0 for simulation, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`ModulePrefix` — Prefix for generated module names
`''` (default) | `'prefix'`

Prefix for generated module names, specified as a character vector or string scalar.

Data Types: char | string

`ReservedWordPostfix` — Postfix for reserved word conflicts
`"_rsvd"` (default) | `"postfix"`

Postfix appended to names that conflict with reserved words in the target language, specified as a character vector or string scalar.

Data Types: char | string

`UserComment` — User comment to include in generated file header
`''` (default) | `"comment text"`

User-specified comment to include in the header of the generated files, specified as a character vector or string scalar.

Data Types: char | string

Optimizations

`MapPersistentVarsToRAM` — Option to map persistent variables to RAM
`true` or `1` (default) | `false` or `0`

Option to map persistent arrays that exceed the RAM threshold to RAM in the generated HLS code, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

`RAMThreshold` — RAM mapping threshold
`"256"` (default)

RAM mapping threshold in bits, specified as a character vector or string scalar. Persistent arrays with a size greater than this threshold are mapped to RAM when MapPersistentVarsToRAM is true.

Data Types: char | string

`ReuseCommonOperations` — Option to reuse common operations
`false` or `0` (default) | `true` or `1`

Option to reuse common operations in the generated HLS code to reduce area, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Advanced Coding

`CodeReplacementLibrary` — Code replacement library name
`"None"` (default) | `"library name"`

Code replacement library name, specified as a character vector or string scalar. Use code replacement libraries to replace MATLAB functions and operators with custom C/C++ implementations in the generated HLS code.

Data Types: char | string

`CustomTclFile` — Custom Tcl file for synthesis scripts
`''` (default) | `"Tcl file name"`

Custom Tcl file name containing additional Tcl commands to include in the generated synthesis scripts, specified as a character vector or string scalar. The custom Tcl commands are sourced near the end of the generated script, so your custom commands take precedence over other Tcl commands earlier in the script.

Data Types: char | string

`InstantiateFunctions` — Option to instantiate functions as separate modules
`false` or `0` (default) | `true` or `1`

Option to instantiate MATLAB functions as separate modules in the generated HLS code, specified as a numeric or logical 1 (true) or 0 (false). When true, MATLAB package hierarchies are mapped to C++ namespaces in the generated HLS code.

Data Types: logical

`RowMajor` — Option to use row-major array layout
`false` or `0` (default) | `true` or `1`

Option to generate HLS code that uses row-major array layout, specified as a numeric or logical 1 (true) or 0 (false). When false, the generated code uses column-major array layout. Row-major layout can improve performance for algorithms that access arrays along rows.

Data Types: logical

`SaturateOnIntegerOverflow` — Option to saturate on integer overflow
`true` or `1` (default) | `false` or `0`

Option to saturate on integer overflow instead of wrapping, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

TestBench

`FPToleranceStrategy` — Floating-point tolerance strategy for test bench verification
`"Relative Error"` (default) | `"Absolute Error"`

Floating-point tolerance strategy used during test bench verification to compare generated code outputs with MATLAB reference outputs, specified as a character vector or string scalar.

Example: "Absolute Error"

Data Types: char | string

`FPToleranceValue` — Floating-point tolerance value for test bench verification
1e-07 (default)

Floating-point tolerance value used during test bench verification, specified as a nonnegative scalar. The tolerance is applied using the strategy specified by FPToleranceStrategy.

Data Types: double

`SimulationIterationLimit` — Maximum number of simulation iterations
-1 (default)

Maximum number of simulation iterations for test bench verification, specified as an integer. A value of -1 means no limit, and all test bench iterations are simulated.

Data Types: double

`UseFiAccelForTestBench` — Option to use `fiaccel` for test bench
`false` or `0` (default) | `true` or `1`

Option to use fiaccel to accelerate fixed-point test bench execution, specified as a numeric or logical 1 (true) or 0 (false).

Data Types: logical

Examples

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Generate HLS Code from a MATLAB Design

Create an HLS configuration object with default settings.

cfg = coder.config("hls");

Set the test bench name.

cfg.TestBenchName = "myDesign_tb";

Generate HLS code for the design function myDesign.

codegen -config cfg myDesign -report

Generate HLS Code with Test Bench Verification

Create an HLS configuration object.

cfg = coder.config("hls");

Configure the object to generate an HLS test bench and verify the generated code.

cfg.TestBenchName = "myFilter_tb";
cfg.GenerateHLSTestBench = true;
cfg.SimulateGeneratedCode = true;

Generate and verify HLS code.

codegen -config cfg myFilter -report

Generate and Synthesize HLS Code

Create an HLS configuration object and configure synthesis options.

cfg = coder.config("hls");
cfg.TestBenchName = "myDesign_tb";
cfg.SynthesisTool = "Xilinx Vitis HLS";
cfg.SynthesisToolChipFamily = "Virtex7";
cfg.SynthesisToolDeviceName = "xc7vx485t";
cfg.SynthesisToolPackageName = "ffg1761";
cfg.SynthesisToolSpeedValue = "-2";
cfg.TargetFrequency = 200;

Enable synthesis of the generated code.

cfg.SynthesizeGeneratedCode = true;

Generate and synthesize HLS code.

codegen -config cfg myDesign -report

Convert `coder.HdlConfig` object to `coder.HlsConfig` object

If you have an existing coder.HdlConfig object configured for the HLS workflow, convert it to coder.HlsConfig.

hdlCfg = coder.config("hdl");
hdlCfg.Workflow = "High Level Synthesis";
hlsCfg = convertToHlsConfig(hdlCfg);

Generate HLS code using the converted configuration object.

codegen -config hlsCfg myDesign -report

Alternatives

You can also generate HLS code from MATLAB code using the HDL Workflow Advisor. For more information, see Get Started with MATLAB to High-Level Synthesis Workflow Using HDL Coder App.

Version History

Introduced in R2026b

expand all

Migration from `coder.HdlConfig`

In releases before R2026b, HLS code generation was configured by using a coder.HdlConfig object with the Workflow property set to "High Level Synthesis". Starting in R2026b, use coder.HlsConfig instead. In a future release, using coder.HdlConfig for HLS code generation will cause an error.

To convert an existing coder.HdlConfig object to coder.HlsConfig, use the convertToHlsConfig function.

coder.HlsConfig

Description

Creation

Syntax

Description

Properties

Report

GenerateCodeReplacementReport — Option to generate a code replacement report false or 0 (default) | true or 1

GenerateReport — Option to generate code generation report false or 0 (default) | true or 1

LaunchReport — Option to open code generation report false or 0 (default) | true or 1

ReportInfoVarName — Name of variable to store report information '' (default) | "variable name"

Comments

GenerateComments — Option to include comments in generated code true or 1 (default) | false or 0

MATLABSourceComments — Option to include MATLAB source code as comments false or 0 (default) | true or 1

General

DesignFunctionName — Name of the design function '' (default) | "function name"

EnableTraceability — Option to enable traceability between MATLAB code and generated HLS code true or 1 (default) | false or 0

GenerateResourceReport — Option to generate a resource utilization report true or 1 (default) | false or 0

TargetLanguage — Target language of the generated code "SystemC" (default)

TestBenchName — Test bench function name '' (default) | "test bench name"

Workflow — HLS code generation workflow "Generic ASIC/FPGA" (default)

Workflow

CheckConformance — Option to check design conformance false or 0 (default) | true or 1

GenerateHLSCode — Option to generate HLS code true or 1 (default) | false or 0

GenerateHLSTestBench — Option to generate an HLS test bench false or 0 (default) | true or 1

HLSTestBenchStimulus — HLS test bench stimulus source "HLS Test bench stimulus" (default)

LaunchConformanceReport — Option to open the conformance report false or 0 (default) | true or 1

SimulateGeneratedCode — Option to simulate generated code false or 0 (default) | true or 1

SynthesizeGeneratedCode — Option to synthesize generated code false or 0 (default) | true or 1

IP Core Options

BitstreamBuildMode — Bitstream build mode "Internal" (default)

BuildBitstream — Option to build bitstream false or 0 (default) | true or 1

CreateEmbeddedSystemProject — Option to create an embedded system project false or 0 (default) | true or 1

EmbeddedSystemTool — Embedded system tool "Xilinx PlanAhead with Embedded Design" (default)

ExecutionMode — IP core execution mode "Free running" (default)

GenerateHostInterfaceScript — Option to generate a host interface script false or 0 (default) | true or 1

IPAddress — IP address of target device "192.168.1.101" (default)

IPCoreName — IP core name '' (default) | "IP core name"

IPCoreVendorName — IP core vendor name '' (default) | "vendor name"

IPCoreVersion — IP core version '' (default) | "version"

ProgramTargetDevice — Option to program the target device false or 0 (default) | true or 1

ProgrammingMethod — Programming method for the target device "Download" (default)

ReferenceDesign — Reference design name '' (default) | "reference design name"

ReferenceDesignPath — Path to the reference design '' (default) | "path"

SSHPassword — SSH password for target device "root" (default)

SSHUsername — SSH username for target device "root" (default)

TargetPlatform — Target platform name '' (default) | "platform name"

Target Tool Selection

SynthesisTool — Synthesis tool name '' (default) | "AMD Vitis HLS" | "Cadence Stratus HLS"

SynthesisToolChipFamily — Synthesis target chip family name '' (default) | "family name"

SynthesisToolDeviceName — Synthesis target device name '' (default) | "device name"

SynthesisToolPackageName — Synthesis target package name '' (default) | "package name"

SynthesisToolSpeedValue — Synthesis target speed value '' (default) | "speed value"

TargetFrequency — Target clock frequency in MHz 0 (default)

Code Style

ComplexImagPostfix — Postfix for imaginary part of complex signals "_im" (default) | "postfix"

ComplexRealPostfix — Postfix for real part of complex signals "_re" (default) | "postfix"

DateComment — Option to include date and time in generated file header true or 1 (default) | false or 0

GenerateHLSCodeRegions — Option to generate HLS code regions false or 0 (default) | true or 1

InitializeBlockRAM — Option to initialize block RAM true or 1 (default) | false or 0

ModulePrefix — Prefix for generated module names '' (default) | 'prefix'

ReservedWordPostfix — Postfix for reserved word conflicts "_rsvd" (default) | "postfix"

UserComment — User comment to include in generated file header '' (default) | "comment text"

Optimizations

MapPersistentVarsToRAM — Option to map persistent variables to RAM true or 1 (default) | false or 0

RAMThreshold — RAM mapping threshold "256" (default)

ReuseCommonOperations — Option to reuse common operations false or 0 (default) | true or 1

Advanced Coding

CodeReplacementLibrary — Code replacement library name "None" (default) | "library name"

CustomTclFile — Custom Tcl file for synthesis scripts '' (default) | "Tcl file name"

InstantiateFunctions — Option to instantiate functions as separate modules false or 0 (default) | true or 1

RowMajor — Option to use row-major array layout false or 0 (default) | true or 1

SaturateOnIntegerOverflow — Option to saturate on integer overflow true or 1 (default) | false or 0

TestBench

FPToleranceStrategy — Floating-point tolerance strategy for test bench verification "Relative Error" (default) | "Absolute Error"

FPToleranceValue — Floating-point tolerance value for test bench verification 1e-07 (default)

SimulationIterationLimit — Maximum number of simulation iterations -1 (default)

UseFiAccelForTestBench — Option to use fiaccel for test bench false or 0 (default) | true or 1

Examples

Generate HLS Code from a MATLAB Design

`GenerateCodeReplacementReport` — Option to generate a code replacement report
`false` or `0` (default) | `true` or `1`

`GenerateReport` — Option to generate code generation report
`false` or `0` (default) | `true` or `1`

`LaunchReport` — Option to open code generation report
`false` or `0` (default) | `true` or `1`

`ReportInfoVarName` — Name of variable to store report information
`''` (default) | `"variable name"`

`GenerateComments` — Option to include comments in generated code
`true` or `1` (default) | `false` or `0`

`MATLABSourceComments` — Option to include MATLAB source code as comments
`false` or `0` (default) | `true` or `1`

`DesignFunctionName` — Name of the design function
`''` (default) | `"function name"`

`EnableTraceability` — Option to enable traceability between MATLAB code and generated HLS code
`true` or `1` (default) | `false` or `0`

`GenerateResourceReport` — Option to generate a resource utilization report
`true` or `1` (default) | `false` or `0`

`TargetLanguage` — Target language of the generated code
`"SystemC"` (default)

`TestBenchName` — Test bench function name
`''` (default) | `"test bench name"`

`Workflow` — HLS code generation workflow
`"Generic ASIC/FPGA"` (default)

`CheckConformance` — Option to check design conformance
`false` or `0` (default) | `true` or `1`

`GenerateHLSCode` — Option to generate HLS code
`true` or `1` (default) | `false` or `0`

`GenerateHLSTestBench` — Option to generate an HLS test bench
`false` or `0` (default) | `true` or `1`

`HLSTestBenchStimulus` — HLS test bench stimulus source
`"HLS Test bench stimulus"` (default)

`LaunchConformanceReport` — Option to open the conformance report
`false` or `0` (default) | `true` or `1`

`SimulateGeneratedCode` — Option to simulate generated code
`false` or `0` (default) | `true` or `1`

`SynthesizeGeneratedCode` — Option to synthesize generated code
`false` or `0` (default) | `true` or `1`

`BitstreamBuildMode` — Bitstream build mode
`"Internal"` (default)

`BuildBitstream` — Option to build bitstream
`false` or `0` (default) | `true` or `1`

`CreateEmbeddedSystemProject` — Option to create an embedded system project
`false` or `0` (default) | `true` or `1`

`EmbeddedSystemTool` — Embedded system tool
`"Xilinx PlanAhead with Embedded Design"` (default)

`ExecutionMode` — IP core execution mode
`"Free running"` (default)

`GenerateHostInterfaceScript` — Option to generate a host interface script
`false` or `0` (default) | `true` or `1`

`IPAddress` — IP address of target device
`"192.168.1.101"` (default)

`IPCoreName` — IP core name
`''` (default) | `"IP core name"`

`IPCoreVendorName` — IP core vendor name
`''` (default) | `"vendor name"`

`IPCoreVersion` — IP core version
`''` (default) | `"version"`

`ProgramTargetDevice` — Option to program the target device
`false` or `0` (default) | `true` or `1`

`ProgrammingMethod` — Programming method for the target device
`"Download"` (default)

`ReferenceDesign` — Reference design name
`''` (default) | `"reference design name"`

`ReferenceDesignPath` — Path to the reference design
`''` (default) | `"path"`

`SSHPassword` — SSH password for target device
`"root"` (default)

`SSHUsername` — SSH username for target device
`"root"` (default)

`TargetPlatform` — Target platform name
`''` (default) | `"platform name"`

`SynthesisTool` — Synthesis tool name
`''` (default) | `"AMD Vitis HLS"` | `"Cadence Stratus HLS"`

`SynthesisToolChipFamily` — Synthesis target chip family name
`''` (default) | `"family name"`

`SynthesisToolDeviceName` — Synthesis target device name
`''` (default) | `"device name"`

`SynthesisToolPackageName` — Synthesis target package name
`''` (default) | `"package name"`

`SynthesisToolSpeedValue` — Synthesis target speed value
`''` (default) | `"speed value"`

`TargetFrequency` — Target clock frequency in MHz
0 (default)

`ComplexImagPostfix` — Postfix for imaginary part of complex signals
`"_im"` (default) | `"postfix"`

`ComplexRealPostfix` — Postfix for real part of complex signals
`"_re"` (default) | `"postfix"`

`DateComment` — Option to include date and time in generated file header
`true` or `1` (default) | `false` or `0`

`GenerateHLSCodeRegions` — Option to generate HLS code regions
`false` or `0` (default) | `true` or `1`

`InitializeBlockRAM` — Option to initialize block RAM
`true` or `1` (default) | `false` or `0`

`ModulePrefix` — Prefix for generated module names
`''` (default) | `'prefix'`

`ReservedWordPostfix` — Postfix for reserved word conflicts
`"_rsvd"` (default) | `"postfix"`

`UserComment` — User comment to include in generated file header
`''` (default) | `"comment text"`

`MapPersistentVarsToRAM` — Option to map persistent variables to RAM
`true` or `1` (default) | `false` or `0`

`RAMThreshold` — RAM mapping threshold
`"256"` (default)

`ReuseCommonOperations` — Option to reuse common operations
`false` or `0` (default) | `true` or `1`

`CodeReplacementLibrary` — Code replacement library name
`"None"` (default) | `"library name"`

`CustomTclFile` — Custom Tcl file for synthesis scripts
`''` (default) | `"Tcl file name"`

`InstantiateFunctions` — Option to instantiate functions as separate modules
`false` or `0` (default) | `true` or `1`

`RowMajor` — Option to use row-major array layout
`false` or `0` (default) | `true` or `1`

`SaturateOnIntegerOverflow` — Option to saturate on integer overflow
`true` or `1` (default) | `false` or `0`

`FPToleranceStrategy` — Floating-point tolerance strategy for test bench verification
`"Relative Error"` (default) | `"Absolute Error"`

`FPToleranceValue` — Floating-point tolerance value for test bench verification
1e-07 (default)

`SimulationIterationLimit` — Maximum number of simulation iterations
-1 (default)

`UseFiAccelForTestBench` — Option to use `fiaccel` for test bench
`false` or `0` (default) | `true` or `1`

Convert `coder.HdlConfig` object to `coder.HlsConfig` object

Migration from `coder.HdlConfig`