setNumberofTriggerStages

R2026b

Configure number of trigger stages for capturing data

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Syntax

setNumberofTriggerStages(DC,N)

Description

Add-On Required: This feature requires the HDL Coder Support Package for Intel FPGA and SoC Devices add-on.

setNumberofTriggerStages(DC,N) specifies an integer value configures the number of trigger stages, N, for capturing data. DC is customized data capture object.

Input Arguments

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Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

Total number of trigger stages in which you want to capture the data, specified as an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool.

Version History

Introduced in R2020b

See Also

Objects

Tools