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hdl.BlackBox

Black box for including custom HDL code

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Description

hdl.BlackBox provides a way to include custom HDL code, such as legacy or handwritten HDL code, in a MATLAB® design intended for HDL code generation.

When you create a user-defined System object™ that inherits from hdl.BlackBox, you specify a port interface and simulation behavior that matches your custom HDL code.

HDL Coder™ simulates the design in MATLAB using the behavior you define in the System object. During code generation, instead of generating code for the simulation behavior, the coder instantiates a module with the port interface you specify in the System object.

To use the generated HDL code in a larger system, you include the custom HDL source files with the rest of the generated code.

To include custom HDL code:

  1. Create the hdl.BlackBox object and set its properties.

  2. Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects?

Creation

Syntax

hdl.BlackBox

Description

Create a System object that inherits from hdl.BlackBox to create a black box for HDL code generation. See Integrate Custom HDL Code Into MATLAB Design.

Properties

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Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects.

Note

You cannot specify clock, reset, and clock enable signals explicitly in your Simulink® model by using the AddClockEnablePort, AddClockPort, and AddResetPort properties. Instead, use these properties to add a clock, reset, or clock enable port in the generated HDL code.

If 'on', add a clock enable input port to the interface generated for the black box System object. The name of the port is specified by ClockEnableInputPort.

If 'on', add a clock input port to the interface generated for the black box System object. The name of the port is specified by ClockInputPort.

If 'on', add a reset input port to the interface generated for the black box System object. The name of the port is specified by ResetInputPort.

If 'on', allow HDL Coder to move registers across the black box System object, from input to output or output to input.

HDL name for clock enable input port, specified as a character vector.

HDL name for clock input port, specified as a character vector.

VHDL® entity, Verilog® module or SystemVerilog module name generated for the black box System object, specified as a character vector.

Example: 'myBlackBoxName'

Latency of black box System object in clock cycles, specified as an integer.

If 0 or greater, this value is used for delay balancing.

If -1, latency is unknown. This disables delay balancing.

When 'on', generate a VHDL configuration.

When 'off', do not generate a VHDL configuration and require a user-supplied external configuration. Set to 'off' if you are creating your own VHDL configuration.

Number of input pipeline stages, or pipeline depth, to insert in the generated code.

Number of output pipeline stages, or output pipeline depth, to insert in the generated code.

HDL name for reset input port, specified as a character vector.

VHDL architecture name, specified as a character vector. The coder generates the architecture name only if InlineConfigurations is 'on'.

Library from which to load the VHDL component, specified as a character vector.

Number of additional input ports in the custom HDL code, specified as a positive integer.

Number of additional output ports in the custom HDL code, specified as a positive integer.

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

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stepRun System object algorithm
releaseRelease resources and allow changes to System object property values and input characteristics
resetReset internal states of System object

Extended Capabilities

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

Introduced in R2015a

See Also

Topics