Generate Multirate HDL Code to Decimate Input Signal Using DSP System Toolbox Blocks
This example shows how to generate HDL code from a model using DSP System Toolbox® blocks. When you generate HDL code from a model using DSP System Toolbox blocks, HDL Coder™ maps Simulink® sample time settings to clock enable signals in generated HDL code.
The model in this example decimates a signal by a factor of 2 using the DSP System Toolbox block FIR Decimation.
load_system('ex_dsp_HDL_generation') open_system('ex_dsp_HDL_generation/DUT')
In this design, the sample rate of the signal after the decimation operation is half the sample rate of the signal before the operation.
When you run makehdl on the DUT, HDL Coder® creates a generated model for code generation, gm_ex_dsp_HDL_generation.slx, and generates HDL code:
makehdl('ex_dsp_HDL_generation/DUT')### Working on the model ex_dsp_HDL_generation ### Generating HDL for ex_dsp_HDL_generation/DUT ### Using the config set for model ex_dsp_HDL_generation for HDL code generation parameters. ### Running HDL checks on the model 'ex_dsp_HDL_generation'. ### Begin compilation of the model 'ex_dsp_HDL_generation'... ### Working on the model 'ex_dsp_HDL_generation'... ### The code generation and optimization options you have chosen have introduced additional pipeline delays. ### The delay balancing feature has automatically inserted matching delays for compensation. ### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays. ### Output port 1: 137 cycles. ### Working on... GenerateModel ### Begin model generation 'gm_ex_dsp_HDL_generation'... ### Rendering DUT with optimization related changes (IO, Area, Pipelining)... ### Model generation complete. ### Generated model saved at hdlsrc/ex_dsp_HDL_generation/gm_ex_dsp_HDL_generation.slx ### Begin VHDL Code Generation for 'ex_dsp_HDL_generation'. ### Begin VHDL Code Generation for 'DUT_tc'. ### Working on DUT_tc as hdlsrc/ex_dsp_HDL_generation/DUT_tc.vhd. ### Code Generation for 'DUT_tc' completed. ### Working on ex_dsp_HDL_generation/DUT/FIR Decimation/nfp_mul_double as hdlsrc/ex_dsp_HDL_generation/nfp_mul_double.vhd. ### Working on ex_dsp_HDL_generation/DUT/FIR Decimation/nfp_add_double as hdlsrc/ex_dsp_HDL_generation/nfp_add_double.vhd. ### Working on ex_dsp_HDL_generation/DUT/FIR Decimation/nfp_add_double as hdlsrc/ex_dsp_HDL_generation/nfp_add_double_block.vhd. ### Working on ex_dsp_HDL_generation/DUT/FIR Decimation as hdlsrc/ex_dsp_HDL_generation/FIR_Decimation.vhd. ### Working on ex_dsp_HDL_generation/DUT as hdlsrc/ex_dsp_HDL_generation/DUT.vhd. ### Generating package file hdlsrc/ex_dsp_HDL_generation/DUT_pkg.vhd. ### Code Generation for 'ex_dsp_HDL_generation' completed. ### Generating HTML files for code generation report at index.html ### Creating HDL Code Generation Check Report DUT_report.html ### HDL check for 'ex_dsp_HDL_generation' complete with 0 errors, 1 warnings, and 0 messages. ### HDL code generation complete.
The Code Generation Report shows the results of code generation.
To learn more about using HDL Coder to generate code from models that use DSP System Toolbox, see HDL Code Generation (DSP System Toolbox).
See Also
FIR Decimation (DSP System Toolbox)
Topics
- Code Generation from Multirate Models
- HDL Code Generation (DSP System Toolbox)
- Multichannel FIR Filter for FPGA (DSP System Toolbox)
