Get Started with Device Trees

A device tree is a data structure that describes hardware devices to the operating system running on the target board. The operating system kernel uses the device tree description to manage the available hardware devices. For example, the operating system uses the device tree to load the specific device driver for a given hardware device.

The device tree has a tree data structure format consisting of nodes and properties. The image shows these components of a device tree.

In the device tree:

This image shows an example device tree. The left side shows the device tree source file. The right side shows a conceptual diagram of the tree structure with nodes and properties. The names of the boxes represent the node names and the text in the box represents the property-value pairs of the nodes.

Use Device Trees with IP Core Generation Workflow

When you deploy a hardware/software design to a SoC device, the device tree informs the PS about IP cores available in the bitstream. The IP cores appear to the PS as devices, which can be accessed from the software application by using device drivers. Therefore, the device tree and bitstream must be synchronized.

You can generate device tree nodes corresponding to the generated IP core by using the IP core generation workflow. The workflow keeps the device tree and bitstream in sync by updating the device tree whenever your IP core changes.

To enable generation of device tree nodes for the HDL Coder generated IP cores, HDL Coder separates the device tree into three distinct segments:

This image shows an SoC board with its individual device tree segments.

When you deploy your design to the target, HDL Coder automatically combines these segments together into a complete device tree that is used to program the target. These sections walk you through the process of registering and generating the different segments of your device tree.

Deploy Device Tree and Bitstream

Download the generated device tree and bitstream for your custom board, reference design, and IP core to the target device by using the HDL Coder IP core generation workflow. The IP core generation workflow compiles the board, reference design, and IP core device trees into a single device tree and then programs them onto the target device along with the generated bitstream. This image shows the generated device tree and bitstream programmed onto the target device.

During the download, HDL Coder uses the device tree compiler on the target board to combine the board device tree, reference design device tree, and IP core device tree. HDL Coder then copies the compiled device tree files back to your host computer.

The following device tree files are generated during the IP Core Generation workflow:

The image shows the folder location of the generated device tree files for a sample IP core.

Sample Device Tree

The image shows your reference design file with the interface details. On the left is an example of a reference design file with interface details. On the right is the generated device tree file.