在自定义硬件上部署 IP 核

通过定义自定义板和参考设计将生成的 IP 核集成到目标 SoC 器件、Speedgoat^® I/O 模块或独立的 FPGA 板中

HDL Coder™ 支持有限数量的预先存在的目标平台。对于快速原型，可以使用预先存在的板，但对于生产，通常需要自定义平台。创建一个自定义平台以将 IP 核集成到独立 FPGA 板或具有 Xilinx^® Vivado^® IP Integrator 或 Intel^® Qsys 的 SoC 平台中。

您可以在 MATLAB^® 中创建自己的自定义参考设计，并使用 HDL Coder 将 IP 核集成到参考设计中。

有关工作流的更多详细信息，请参阅Targeting FPGA & SoC Hardware Overview。

Create a custom hardware platform workflow

类

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

函数

全部展开

板和参考设计

`addCustomEDKDesign`	Specify Xilinx EDK MHS project file
`addCustomQsysDesign`	Specify Altera Qsys project file
`addCustomVivadoDesign`	Specify Xilinx Vivado exported block design Tcl file
`addCustomLiberoDesign`	Specify Microchip Libero SoC exported block design Tcl file (自 R2022b 起)
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

添加接口

`addEthernetMACInterface`	Define Ethernet MAC interface for board object (自 R2022b 起)
`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addFPGADataCaptureInterface`	Add and define FPGA Data Capture interface (自 R2025a 起)
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addAXI4SlaveInterface`	Add and define AXI4 slave interface
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface
`addMemoryInterface`	Access memory regions on your FPGA or SoC hardware (自 R2023a 起)

回调函数

`CallbackCustomProgrammingMethod`	Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
`CustomizeReferenceDesignFcn`	Function handle for callback function that gets executed before Set Target Interface task in the HDL Workflow Advisor
`EmbeddedCoderSupportPackage`	Specify whether to use an Embedded Coder support package
`PostBuildBitstreamFcn`	Function handle for callback function that gets executed after the build FPGA bitstream task runs
`PostCreateProjectFcn`	Function handle for callback function that gets executed after the create project task runs
`PostSWInterfaceFcn`	Function handle for custom callback function that gets executed after the generate software interface task runs
`PostTargetInterfaceFcn`	Function handle for callback function that gets executed after the set target interface task runs
`PostTargetReferenceDesignFcn`	Function handle for callback function that gets executed after the target reference design is set

设备树生成

`addDeviceTree`	Add device tree for board object (自 R2021b 起)
`addDeviceTreeIncludeDirectory`	Specify the path of an include file to compile the device tree against (自 R2021b 起)
`addDeviceTree`	Add device tree for reference design object (自 R2021b 起)
`addDeviceTreeIncludeDirectory`	Specify the path of an include file to compile the device tree against (自 R2021b 起)

导出参考设计

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor

主题

板和参考设计

Board and Reference Design Registration System
System for defining and registering boards and reference designs.
Register a Custom Board
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Register a Custom Reference Design
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Define Custom Parameters and Callback Functions for Custom Reference Design
Learn how to define custom parameters and custom callback functions for your custom reference design.
Customize Reference Design Dynamically Based on Reference Design Parameters
Learn how to customize the reference design dynamically by using the CustomizeReferenceDesignFcn method.
Define and Add IP Repository to Custom Reference Design
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.
Define Multiple AXI Master Interfaces in Reference Designs to Access DUT AXI4 Slave Interface
Learn how you can specify multiple AXI Master interfaces in the custom reference design to access HDL DUT IP AXI4 slave interface.
Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces
Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces.
Use Callback Functions in Custom Reference Design
This example illustrates how to customize the reference design dynamically by using a callback function based on the reference design parameter options.
IP Caching for Faster Reference Design Synthesis
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.
Generate Device Tree for IP Core
Generate device tree files that include the HDL Coder generated IP core.
Export Custom Reference Design from SoC Model (SoC Blockset)
Use the socExportReferenceDesign function to export a custom reference design from an SoC Blockset™ model.

特定硬件平台

Define Custom Board and Reference Design for AMD Workflow
This example shows how to define and register a custom board and custom reference design in the Zynq® workflow.
Build Custom Linux Image for HDL Coder IP Core
This example shows how to build a custom Zynq® Linux® image for a Digilent™ Zybo™ Z7-10 Zynq board by using the MathWorks® build system.
Define Custom Board and Reference Design for Intel Workflow
This example shows how to define and register a custom board and reference design in the HDL Coder™ Intel® SoC workflow.
Define Custom Board and Reference Design for Microchip Workflow
This example shows how to define and register a custom board and reference design for a blinking LED model in the Microchip workflow of the HDL Workflow Advisor.
Define Custom Board and Reference Design for Pure Microchip FPGA Workflow
Define and register Pure FPGA boards and reference designs for an LED blinking model using Microchip Polarfire^® in the HDL Workflow Advisor.
Define Custom Board and Reference Design for Zynq Ultrascale+ MPSoC Workflow
This example shows how to define and register a custom board and reference design for the Zynq® workflow using a Xilinx® Zynq UltraScale+™ MPSoC ZCU104 evaluation kit.
Build Custom Reference Design to Interface with Peripheral Chip
This example shows how to build a reference design to run an audio algorithm and access audio input and output on a Zynq® board.
Authoring a Reference Design for Audio System on a ZYBO Board
This example shows how to build a reference design to run an audio algorithm and access audio input and output on ZYBO™ Z7-10 board.
Author Audio System Reference Design for Basic Intel Evaluation Board
This example shows how to build a reference design to run an audio algorithm and access audio input and output on an Intel® Arrrow® SoC board.