Using Triggered Subsystems for HDL Code Generation

The Triggered Subsystem block is a Subsystem block that executes each time the control signal has a trigger value. To learn more about the block, see Triggered Subsystem.

Best Practices

When using triggered subsystems in models targeted for HDL code generation, consider the following:

For synthesis results to match Simulink^® results, drive the trigger port with registered logic (with a synchronous clock) on the FPGA.
It is good practice to put unit delays on Triggered Subsystem output signals. Doing so prevents the code generator from inserting extra bypass registers in the HDL code.
The use of triggered subsystems can affect synthesis results in the following ways:
- In some cases, the system clock speed can drop by a small percentage.
- Generated code uses more resources, scaling with the number of triggered subsystem instances and the number of output ports per subsystem.

Using the Signal Editor Block

When you connect outputs from a Signal Editor block to a triggered subsystem, you might need to use a Rate Transition block. To run all triggered subsystem ports at the same rate:

If the trigger source is a Signal Editor block, but the other triggered subsystem inputs come from other sources, insert a Rate Transition block into the signal path before the trigger input.
If all inputs (including the trigger) come from a Signal Editor block, they have the same rate, so special action is not required.

Using Trigger As Clock

Using the trigger as clock in triggered subsystems enables you to partition your design into different clock regions in the generated code. Make sure that the Clock edge setting in the Configuration Parameters dialog box matches the Trigger type of the Trigger block inside the triggered subsystem.

For example, you can model:

A design with clocks that run at the same rate, but out of phase.
Clock regions driven by an external or internal clock divider.
Clock regions driven by clocks whose rates are not integer multiples of each other.
Internally generated clocks.
Clock gating for low-power design.

Note

Using the trigger as clock for triggered subsystems can result in timing mismatches of one cycle during testbench simulation.

Specify Trigger As Clock

In HDL Code Generation > Global Settings > Ports tab, select Use trigger signal as clock.
Set the TriggerAsClock property using makehdl or hdlset_param. For example, to generate HDL code that uses the trigger signal as clock for triggered subsystems in a DUT subsystem, myDUT, in a model, myModel, enter:
```
makehdl ("myModel/myDUT",TriggerAsClock="on")
```

Trigger As Clock Without Synchronous Registers

When you use the trigger as clock in triggered subsystem, each triggered subsystem input or output requires synchronization delays immediately outside and immediately inside the subsystem. These delays act as a synchronization interface between the regions running at different rates. HDL Coder™ can allows you to generate HDL code without adding the synchronization delays by enabling the "trigger as clock without synchronous register" option. By default, this option is on.

You can enable or disable this option by using makehdl or hdlset_param function. For example, to generate an HDL code for a DUT subsystem, myDUT in a model, myModel, that uses trigger as a clock for triggered subsystem without having synchronization delays, enter:

makehdl("myModel/myDUT",TriggerAsClockWithoutSyncRegisters="on")

Model Trigger Signal As Clock in Triggered Subsystem

Open Script

This example shows how to model trigger port of the Triggered Subsystem as a clock signal. Using trigger as clock functionality in the Triggered Subsystem enables you to use trigger signal as a clock in your generated HDL code.

The model TriggerAsClockSingle has a DUT subsystem which contains a Triggered Subsystem. Load and open the TriggerAsClockSingle model by running these commands:

load_system("TriggerAsClockSingle");
set_param("TriggerAsClockSingle",'SimulationCommand','Update')
open_system("TriggerAsClockSingle/DUT");

To use trigger signal as clock in your generated HDL code, enable Use trigger signal as clock option in the HDL Code Generation > Global Settings > Ports tab of the configuration settings. Then, generate the HDL code for a DUT subsystem using makehdl command or HDL Coder™ app:

makehdl("TriggerAsClockSingle/DUT")

In the generated HDL code, HDL Coder maps the trigger port of the Triggered Subsystem to the clock. This code snippet shows the HDL code of Triggered Subsystem which uses Trigger signal as a clock.

     Delay1_process : PROCESS (Trigger, reset)
     BEGIN
         IF reset = '1' THEN
             Delay1_out1 <= to_unsigned(16#0000#, 16);
         ELSIF Trigger'EVENT AND Trigger = '1' THEN
             Delay1_out1 <= Gain_out1;
         END IF;
     END PROCESS Delay1_process;

Use Triggered and Resettable Subsystem to Model Clock and Reset Signals

You can model control signals, such as clock and reset, by using the triggered and resettable subsystem. You can use trigger as clock functionality to model trigger port from triggered subsystem as a clock and use resettable subsystem to model reset port from Simulink.

When you use triggered or resettable subsystem in your model targeted for HDL code generation, you can:

Model a clock and reset signal from Simulink by including a resettable subsystem inside the triggered subsystem.
Use a triggered subsystem with synchronous semantics.
Generate a code with a single clock and reset for a nested resettable subsystem inside a triggered subsystem by using the Use trigger signal as clock and Minimize global resets parameters.
Generate code that has multiple clock and reset signals for a model consisting of multiple triggered and resettable subsystem.
Use Unit Delay Enabled Synchronous block inside the Triggered subsystem.
Model a Unit Delay Resettable Synchronous block in the triggered subsystem by adding the Unit Delay block to a resettable subsystem with synchronous semantics and placing the resettable subsystem inside triggered subsystem.
Model a Unit Delay Enabled Resettable Synchronous block in the triggered subsystem by adding the Unit Delay Enabled block to a resettable subsystem with synchronous semantics and placing the resettable subsystem inside triggered subsystem.

Model Single Clock and Reset Signal Using Triggered and Resettable Subsystems

Open Script

This example shows how to model clock and reset signal using Triggered and Resettable subsystems. You can use trigger as clock functionality to model trigger port from triggered subsystem as a clock and use resettable subsystem to model reset port.

The model ClockAndResetModellingUsingTriggerAsClock has a DUT subsystem which contains a Triggered Subsystem. Load and open the ClockAndResetModellingUsingTriggerAsClock model by running these commands:

load_system("ClockAndResetModellingUsingTriggerAsClock");
set_param("ClockAndResetModellingUsingTriggerAsClock",'SimulationCommand','Update')
open_system("ClockAndResetModellingUsingTriggerAsClock/DUT");

A resettable subsystem is placed within the triggered subsystem. Using resettable subsystem, you can model a reset port for your model. Minimize the global reset option so that model has single reset signal from resettable subsystem. To minimize global reset option, enable Minimize global resets in the HDL Code Generation > Global Settings > Ports tab of the configuration settings.

To use trigger signal as clock in your generated HDL code, enable Use trigger signal as clock option in the HDL Code Generation > Global Settings > Ports tab. Then, generate the HDL code for a DUT subsystem using makehdl command or HDL Coder™ app:

makehdl("ClockAndResetModellingUsingTriggerAsClock/DUT")

In the generated HDL code, HDL Coder maps the trigger port of the Triggered Subsystem to the clock. Also, the reset signal is generated from the Resettable subsystem. The HDL code of triggered subsystem shows mapping of trigger port to clock signal in the resettable subsystem.

     module Triggered_Subsystem
                 (Trigger,
                 Reset_1,
                 Input_Data,
                 Output_rsvd);

         input   Trigger;
         input   Reset_1;
         input   [1:0] Input_Data;  // ufix2
         output  [3:0] Output_rsvd;  // ufix4

         wire [3:0] Resettable_Subsystem_out1;  // ufix4

         Resettable_Subsystem u_Resettable_Subsystem (.clk(Trigger),
                                                     .Input_Data(Input_Data),  // ufix2
                                                     .Reset_1(Reset_1),
                                                     .Output_rsvd(Resettable_Subsystem_out1)  // ufix4
                                                     );
         assign Output_rsvd = Resettable_Subsystem_out1;

     endmodule  // Triggered_Subsystem

Limitations

HDL Coder supports HDL code generation for triggered subsystems that meet the following conditions:

The triggered subsystem is not the DUT.
The subsystem is not both triggered and enabled.
The trigger signal is a scalar.
If the output of the subsystem is a bus then initial value of the outport must be 0.
All inputs and outputs of the triggered subsystem (including the trigger signal) run at the same rate.
The Show output port parameter of the Trigger block is set to Off.
The Latch input by delaying outside signal check box is not selected on the Inport block inside the Triggered Subsystem.
If the DUT contains the following blocks, RAMArchitecture is set to WithClockEnable:
- Dual Port RAM
- Simple Dual Port RAM
- Single Port RAM
The triggered subsystem does not contain the following blocks:
- Discrete-Time Integrator
- CIC Decimation
- CIC Interpolation
- FIR Decimation
- FIR Interpolation
- Downsample
- Upsample
- HDL Cosimulation blocks for HDL Verifier™
- Rate Transition
- Pixel Stream FIFO (Vision HDL Toolbox™)
- PN Sequence Generator, if the Use trigger signal as clock option is selected.