Generate Multiple Clocks Using Trigger As Clock

This example shows how to model multiple clock signals using triggered subsystems. Using trigger as clock functionality in the triggered subsystem enables you to use trigger signal as a clock in your generated HDL code. You can model an asynchronous clock domain design in Simulink® by using multiple triggered subsystem and use trigger as a clock functionality to generate separate clock signal for each triggered subsystem.

The model AsynchronousClockUsingTriggerAsClock has a DUT subsystem which contains a two Triggered Subsystem. Load and open the AsynchronousClockUsingTriggerAsClock model by running these commands:

load_system("AsynchronousClockUsingTriggerAsClock");
set_param("AsynchronousClockUsingTriggerAsClock",'SimulationCommand','Update')
open_system("AsynchronousClockUsingTriggerAsClock/DUT");

To use trigger signal as clock in your generated HDL code, enable Use trigger signal as clock option in the HDL Code Generation > Global Settings > Ports tab of the configuration settings. Then, generate the HDL code for a DUT subsystem using makehdl command or HDL Coder™ app:

makehdl("AsynchronousClockUsingTriggerAsClock/DUT")

In the generated HDL code, HDL Coder generates two trigger ports for the DUT subsystem which are used as clock signal in the triggered subsystems.

         module DUT
                 (Trigger1,
                 Trigger2,
                 Data,
                 Out1);

         input   Trigger1;
         input   Trigger2;
         input   [1:0] Data;  // ufix2
         output  [7:0] Out1;  // uint8

         wire [7:0] Triggered_Subsystem1_out1;  // uint8
         wire [7:0] Triggered_Subsystem2_out1;  // uint8

         Triggered_Subsystem1 u_Triggered_Subsystem1 (.Trigger(Trigger1),
                                                     .In1(Data),  // ufix2
                                                     .Out1(Triggered_Subsystem1_out1)  // uint8
                                                     );

         Triggered_Subsystem2 u_Triggered_Subsystem2 (.Trigger(Trigger2),
                                                     .In1(Triggered_Subsystem1_out1),  // uint8
                                                     .Out1(Triggered_Subsystem2_out1)  // uint8
                                                     );

         assign Out1 = Triggered_Subsystem2_out1;

     endmodule  // DUT

Each triggered subsystem is driven by the separate clock connected to the trigger port of triggered subsystem. You can use these clock signals to operate the subsystems at different clock rates. In the HDL code for triggered subsystem, the trigger signals are used as clock as shown in code snippet below.

     module Triggered_Subsystem1
                 (Trigger,
                 In1,
                 Out1);

         input   Trigger;
         input   [1:0] In1;  // ufix2
         output  [7:0] Out1;  // uint8
     ...
     ...
     always @(posedge Trigger)
     begin : Delay1_process
         Delay1_out1 <= Gain_out1;
     end

load_system("PhasedClocksUsingTriggeredSubsystem");
set_param("PhasedClocksUsingTriggeredSubsystem",'SimulationCommand','Update')
open_system("PhasedClocksUsingTriggeredSubsystem");

open_system("PhasedClocksUsingTriggeredSubsystem/Phased_Clock_DUT");

Generate Multiple Clocks and Resets Using Triggered and Resettable Subsystems

This example shows how to model multiple clock and reset signals using triggered and resettable subsystems. Using trigger as clock functionality, you can model multiple clock signals from multiple triggered subsystems. By placing the resettable subsystem inside each triggered subsystem, you can model multiple reset signals in your Simulink model.

load_system("AsynchronousClockandResetUsingTriggerAsClock");
set_param("AsynchronousClockandResetUsingTriggerAsClock",'SimulationCommand','Update')
open_system("AsynchronousClockandResetUsingTriggerAsClock/DUT");

makehdl("AsynchronousClockandResetUsingTriggerAsClock/DUT")

     ENTITY DUT IS
       PORT( Trigger1                          :   IN    std_logic;
             Trigger2                          :   IN    std_logic;
             Data                              :   IN    std_logic_vector(1 DOWNTO 0);  -- ufix2
             Reset1                            :   IN    std_logic;
             Reset2                            :   IN    std_logic;
             Out2                              :   OUT   std_logic_vector(7 DOWNTO 0)  -- uint8
             );
     END DUT;

     ...
     ...

     BEGIN
         u_Triggered_Subsystem1 : Triggered_Subsystem1
           PORT MAP( Trigger => Trigger1,
                     Data => Data,  -- ufix2
                     Reset1 => Reset1,
                     Out1 => Triggered_Subsystem1_out1  -- ufix2
                     );

         u_Triggered_Subsystem2 : Triggered_Subsystem2
           PORT MAP( Trigger => Trigger2,
                     Data => Triggered_Subsystem1_out1,  -- ufix2
                     Reset2 => Reset2,
                     Out1 => Triggered_Subsystem2_out1  -- uint8
                     );

         Out2 <= Triggered_Subsystem2_out1;

     END rtl;

Model Asynchronous and Synchronous Reset for a Simulink Model

You can generate synchronous and asynchronous external resets for your Simulink model by using nested triggered and resettable subsystems. You can use trigger-as-clock functionality to model the trigger port from a Triggered Subsystem as a clock and use Resettable Subsystem to model external reset port.

always @(posedge Trigger)
    begin : Delay_process
        if (Reset_1 == 1'b1) begin
            Delay_out1 <= 2'b00;
        end
...

always @(posedge Trigger or posedge Reset_1)
    begin : Delay_process
        if (Reset_1 == 1'b1) begin
            Delay_out1 <= 2'b00;
        end
...

always @(posedge Trigger or posedge reset)
    begin : Delay_process
        if (reset == 1'b1) begin
            Delay_out1 <= 2'b00;
        end
        else begin
            if (Reset_1 == 1'b1) begin
                Delay_out1 <= 2'b00;
            end
...