Create IBIS Model from SPICE Simulation Data

Prerequisites: Understand Your Simulation Data

Before launching IBIS Designer, you need simulation output files from your circuit simulator (HSPICE, Spectre, or similar). The SPICE Simulation workflow requires up to four types of data for each process corner:

The AC admittance output (ax_) files provide output-mode capacitance data. For an I/O buffer, this allows separate C_comp extraction for input mode (receiver with high-Z output) and output mode (driver active), giving the simulator more accurate capacitance values for each operating state.

Supported File Formats

IBIS Designer accepts simulation output in several formats depending on the data type:

If you provide binary HSPICE files (.sw0 or .tr0), IBIS Designer automatically converts them to CSV format during processing. The .CSV files are written to a temp directory and deleted when the session is closed. This process requires a Mixed Signal Blockset license.

Cadence Spectre users can point to .raw output directories directly using the Select by Directory option in the Load Files dialog.

Process Corners

Each file type is needed at three process corners:

Alternatively, you can generate a typical-corner-only model if min/max data is not yet available (see the Typical corner only option in the Load Files dialog).

For this example, we use a pre-characterized DDR5 I/O buffer dataset attached to this example. The files follow IBIS Designer's auto-fill naming convention:

{file_type}_{corner}_{modelname}.{ext}

For example: iv_tt_ddr5_dq_io.csv and vt_ss_ddr5_dq_io.csv IV and VT files use .csv format, while the AC admittance files (e.g. ac_ff_ddr5_dq_io.ac0) use the HSPICE ASCII .ac0 format.

For information on generating SPICE simulation data, see the page Generate HSPICE Simulation Decks for IBIS Characterization.

CSV File Format

IBIS Designer expects CSV files to have a three-line header followed by comma-separated numeric data. This three-line header is the default output format produced by the MATLAB sw0Reader, tr0Reader, and ac0Reader functions when converting HSPICE binary files to CSV. The parser skips exactly three lines before reading data, so this structure is required:

If your CSV files come from a source other than HSPICE and do not have the first two lines, you must add them (the content of lines 1 and 2 is not parsed, so only the line count matters). If these lines are missing, the parser will silently skip the column header and the first two rows of data.

Important: The parser determines columns by position, not by header name. When preparing your own CSV files, you must ensure the columns appear in the correct order as described below. This constraint does not apply when using binary HSPICE files (.sw0, .tr0): the sw0Reader and tr0Reader functions read named signals and automatically reorder columns into the expected layout.

IV File Structure

The DC sweep CSV has 7 columns: a sweep-point column, a measured voltage column, and five current columns. All seven are required for I/O models, in this order:

IBIS Designer uses column 2 as the voltage axis for all IV curves. Columns 3-7 provide the currents measured under different bias conditions. The sweep ranges from -Vdd to 2*Vdd (here -1.1 V to 2.2 V), covering the full operating range needed for pulldown IV, pullup IV, GND clamp, and POWER clamp extraction.

If you are using a simulator other than HSPICE: Run a DC sweep of the pad voltage from -Vdd to 2*Vdd and record the six columns above. You need three separate bias conditions (output-low, output-high, high-impedance) plus isolated pullup/pulldown measurements. See the page Generate HSPICE Simulation Decks for IBIS Characterization for the testbench topology that produces each column.

VT File Structure

The transient file contains time and voltage columns for the output node driven into fixture loads. The required column order is:

In this example, the header reads TIME,v(v_stimulus),v(dq_io_gnd),v(dq_io_vdd).

If you are using a simulator other than HSPICE: Run a transient simulation with the buffer driving a 50-ohm resistor to GND (and optionally a second fixture to Vdd). Record time, the input stimulus, and the output voltage at the fixture tap point. See the page Generate HSPICE Simulation Decks for IBIS Characterization for the fixture topology.

AC File Structure

The admittance file uses the HSPICE ASCII .ac0 format (not CSV), which contains a single frequency point with the imaginary part of the input admittance:

#C 100000000 1 0.0005654837 /1

IBIS Designer parses the #C data line to extract the frequency and admittance values. It then computes C_comp as: $$C=Y_{imag}/(2\pi f)$$. A single frequency point at 100 MHz is sufficient for this extraction.

If you are using a simulator other than HSPICE: Run an AC analysis at a single frequency (e.g., 100 MHz) with the buffer in receiver mode (high-impedance output). Measure the imaginary part of the input admittance at the pad. Write the result in the format shown above, or provide a CSV with frequency and imaginary admittance columns.

Setup

Open the IBIS Designer application by calling ibisDesigner at the MATLAB command line.

ibisDesigner

Select File > New > SPICE Simulation from the menu bar. The Load Simulation Files dialog is where you specify your input data. It opens automatically when creating a new session and can be reopened at any time via the Load Files button.

Load Simulation Files

The Load Simulation Files dialog has fields for the model type, dialog options, a simulation directory for bulk auto-fill, and individual file paths for each corner and file type.

Select the Model Type

Set the Model Type dropdown to I/O. This enables all file rows because an I/O buffer needs both driver data (IV, VT) and receiver data (AC for input capacitance). The model type determines which file rows are active:

Note: Additional model types are available from the Model Type dropdown to support many different applications.

Dialog Options

Below the Model Type dropdown, two check boxes control how files are selected:

For this example, leave both check boxes unchecked. We have full three-corner HSPICE data.

Use Auto-Fill to Load Files

Click the Browse button next to the Simulation directory field and navigate to the example directory containing the example simulation files. When you select the directory, IBIS Designer automatically scans for files matching the naming convention {file_type}_{corner}_{modelname}.{ext} and fills all file path fields.

The auto-fill recognizes these corner identifiers:

After auto-fill completes, all 12 file fields are populated as shown in the screenshot below.

Browse for Individual Files

Alternatively, you can populate file paths one at a time using the "..." browse button next to each field. This is useful when your files do not follow the auto-fill naming convention, are spread across different directories, or when you need to override a single file that auto-fill assigned incorrectly. The file picker filters by extension based on the row type: IV rows show .csv and .sw0 files, VT rows show .csv and .tr0 files, and AC/AX rows show .csv and .ac0 files.

Click OK to accept the file assignments. The dialog closes and the main panel's corner table populates with the loaded file paths.

Configure Model Identity

Set the following fields in the IBIS Model section of the left panel:

These fields map directly to IBIS file keywords. When you later use this model in a signal integrity simulator, you reference it by the Model Name and associate it with physical pins via the Pin Number and Signal Name fields.

Differential Configuration

The Differential section provides an optional check box and fields for differential pin pairs. When the Differential check box is enabled, the generated IBIS file includes a two-pin [Pin] table and a [Diff Pin] section that pairs the non-inverting and inverting pins. The fields are:

For this DDR5 single-ended DQ example, leave the Differential check box unchecked. Differential mode is used for signals like DQS (data strobe) or CK (clock) that are routed as complementary pairs.

Set Model Parameters

The Model Parameters section contains receiver thresholds and timing test load values that are written as subparameters of the [Model] keyword in the IBIS file. These parameters allow EDA tools to determine digital switching thresholds and to construct the correct test load for propagation delay measurements. Enter the following values:

These values are specific to DDR5 DQ signaling. For other interface standards, consult the specification for the appropriate threshold and reference levels. If left blank (NaN), the corresponding subparameter is omitted from the IBIS file.

For advanced per-corner parameters (overshoot limits, hysteresis thresholds, edge-specific timing loads), use Options > IBIS Parameters from the menu bar. Those values are written to the [Model Spec] keyword, which can override the [Model]-level values on a per-corner basis. The defaults are sufficient for most applications.

Configure Corner Values

Set the operating conditions for each process corner in the Corner Values section. These values define the temperature and supply voltage that were used during input file generation and will appear in the generated IBIS file:

The IBIS "min" corner represents minimum drive strength (slowest buffer), not minimum voltage. This is why the slow corner has high temperature (increased carrier scattering reduces mobility) and low voltage (less overdrive).

Verify the Temperature values and update the Voltage values to match the table above.

Configure Package RLC

The Package RLC section specifies the parasitic resistance, inductance, and capacitance of the package interconnect between the die pad and the external pin. These values are written to the [Package] keyword in the IBIS file and allow the simulator to model package effects on signal integrity.

Each parameter has Typ, Min, and Max columns corresponding to the three process corners:

For this example, the Package RLC values are set to negligibly small defaults. In a production model, you would obtain these values from the package substrate design (e.g., from a 3D EM extraction tool) and they would vary across corners to reflect manufacturing tolerances. If Min and Max are left blank (NA), only the Typ column is written to the IBIS file.

Set Conversion Options (Optional)

IBIS Designer provides conversion options that control how raw simulation data is processed. For most use cases, the defaults produce correct results. Access these options via Options > Conversion Options from the menu bar.

The dialog is organized into two tabs: IV / VT (extraction parameters) and Edge Detection (transition identification algorithm).

Tab 1: IV / VT Options

The left panel contains IV extraction options:

The right panel contains VT / Ramp extraction options:

Tab 2: Edge Detection Options

These options control how IBIS Designer identifies rising and falling transitions in the VT simulation data. The Edge Mode dropdown selects the detection algorithm:

When Edge Mode is set to Custom, the following options become available:

For this example, leave Edge Mode set to Standard. The defaults are calibrated for standard DDR-style testbench configurations with a 50-ohm fixture, a single rising and falling edge per simulation, and 20%/80% threshold crossings for ramp calculation.

Preview IBIS

Click the Preview IBIS button in the action bar at the bottom of the window. The conversion pipeline performs these steps:

The status bar shows progress. When conversion finishes, the status lamp turns green and shows "Preview complete". The model is now in memory but has not been written to disk yet:

Review Results

After preview, the Visualization panel at the bottom of the window populates with results. Use the tabs to inspect each aspect of the extracted model.

IV Curves

The IV Raw tab shows the IV curves extracted from each corner's DC sweep data. For an I/O buffer, six sub-tabs are available: Pulldown, Pullup, Pullup VR, Power Clamp, Power Clamp VR, and GND Clamp.

Each curve shows typ (blue), min (green), and max (red) corners. The min corner shows reduced current at the same voltage (weaker drive due to higher resistance).

IV Combined

The IV Combined tab shows the total current that a signal integrity simulator would compute at the pad by summing the individual IV components. It has two sub-tabs:

These combined plots show what a receiver would see when the driver is in the low or high state. The clamp currents are negligible in the mid-range (between 0 and Vdd) but become significant near the rails, where the ESD clamp activates. Comparing the combined curves against the raw curves helps verify that the clamp and driver contributions interact correctly.

VT Waveforms

The VT Waveforms tab shows the transient voltage response extracted from the simulation. Four waveforms are generated (with VT_Count = 4), each shown in a sub-tab:

Unlike the Parameterized Model workflow (which generates idealized RC transitions), these waveforms capture the actual nonlinear switching behavior of the transistor-level circuit, including any overshoot, undershoot, or non-monotonic settling.

IBIS Preview

The IBIS Preview tab shows the complete text of the generated IBIS file. Scroll through to verify the structure:

Logs

The Logs tab records a timestamped run history showing validation status, extraction progress, and the results of ibischk validation (if enabled via Options > Always Run IBISCHK). When ibischk runs, the full output including any error or warning messages is appended here.

Validate with IBISCHK (Optional)

Before exporting, you can validate the generated model against the IBIS specification by clicking the IBISCHK button in the action bar. This step is optional and requires a Signal Integrity Toolbox license. If the toolbox is not installed, the button displays an alert indicating that ibischk is not available.

The ibischk validator is the industry-standard compliance checker maintained by the IBIS Open Forum. It parses the generated IBIS file and checks for:

Results appear in the Logs tab of the Visualization panel and in the status bar, which shows a summary such as "Done. ibischk: 0 errors, 2 warnings". If errors are found, the status lamp turns amber and shows "Done with issues."

You can also enable automatic validation after every preview by selecting Options > Always Run IBISCHK from the menu bar. When enabled, IBIS Designer runs ibischk each time you click Preview IBIS, so you get immediate feedback as you iterate on conversion options or corner parameters.

A valid model produced from clean simulation data should show zero errors. Warnings are common and usually informational (for example, noting that optional fields like [Model Spec] are not present).

Export the IBIS File

Click Export IBIS in the action bar to write the generated model to a .ibs file on disk. The file is saved to the Target directory specified in the Output section, using the filename from the IBIS Filename field in the IBIS Model section. If Target directory is blank, the current MATLAB working directory is used.

Save the Session

To preserve your work for later editing, save the session via File > Save (or File > Save As... to choose a new location). The session is stored as a .mat file (default name s2i_session.mat) that captures the complete app state:

You can also use Export > Export to MATLAB to generate a standalone MATLAB script that recreates the current session programmatically. Unlike the session file (which stores internal app state), the exported script uses public API calls and is suitable for version control, automation, or batch processing.

Programmatic Equivalent

The entire workflow demonstrated above can be reproduced programmatically using the IBIS Designer public API. The following script converts the same DDR5 I/O dataset without opening the GUI:

dataDir = pwd;

Configure the Data Object

Create a data container and set the model identity, supply voltage, and corner-specific file paths:

d = ibisDesignerData;
d.ModelName = "ddr5_dq_io";
d.ModelType = "I/O";
d.ComponentName = "DDR5_PHY";
d.ManufacturerName = "Generic";
d.PinName = "A1";
d.SignalName = "DQ0";
d.Vdd = 1.1;

Assign Corner Data

Each corner needs a temperature, voltage, and file paths for IV, VT, and AC data:

d.CornerData(1).Corner = "typ";
d.CornerData(1).Temperature = 25;
d.CornerData(1).Voltage = 1.1;
d.CornerData(1).IVFile = fullfile(dataDir, "iv_tt_ddr5_dq_io.csv");
d.CornerData(1).VTFile = fullfile(dataDir, "vt_tt_ddr5_dq_io.csv");
d.CornerData(1).ACFile = fullfile(dataDir, "ac_tt_ddr5_dq_io.ac0");
d.CornerData(1).AXFile = fullfile(dataDir, "ax_tt_ddr5_dq_io.ac0");
d.CornerData(2).Corner = "min";
d.CornerData(2).Temperature = 100;
d.CornerData(2).Voltage = 1.067;
d.CornerData(2).IVFile = fullfile(dataDir, "iv_ss_ddr5_dq_io.csv");
d.CornerData(2).VTFile = fullfile(dataDir, "vt_ss_ddr5_dq_io.csv");
d.CornerData(2).ACFile = fullfile(dataDir, "ac_ss_ddr5_dq_io.ac0");
d.CornerData(2).AXFile = fullfile(dataDir, "ax_ss_ddr5_dq_io.ac0");
d.CornerData(3).Corner = "max";
d.CornerData(3).Temperature = 0;
d.CornerData(3).Voltage = 1.166;
d.CornerData(3).IVFile = fullfile(dataDir, "iv_ff_ddr5_dq_io.csv");
d.CornerData(3).VTFile = fullfile(dataDir, "vt_ff_ddr5_dq_io.csv");
d.CornerData(3).ACFile = fullfile(dataDir, "ac_ff_ddr5_dq_io.ac0");
d.CornerData(3).AXFile = fullfile(dataDir, "ax_ff_ddr5_dq_io.ac0");

Set Model Parameters

d.Vinl = 0.86;
d.Vinh = 1.06;
d.Vmeas = 0.96;
d.Vref = 1.1;
d.Rref = 50;
d.Cref = 10e-12;

Set Fixture and Package Parameters

d.RFixture = 50;
d.VFixtureGnd = 0;
d.PackageR = [0.001e-3, 0.001e-3, 0.001e-3];
d.PackageL = [1e-12, 1e-12, 1e-12];
d.PackageC = [1e-15, 1e-15, 1e-15];

Validate, Convert, and Write

The validate method checks that all required files exist and parameters are consistent. Then ibisProcessor runs the extraction pipeline and ibisWriter produces the output file:

d.validate();
converter = ibisProcessor(d);
ibisFile = ibisWriter(converter);
ibisFile.writeIBISFile("ddr5_dq_io.ibs");

Validate with IBISCHK

Run the ibischk compliance checker against the exported file (requires Signal Integrity Toolbox):

ibischk("ddr5_dq_io.ibs");

The three-step pipeline (ibisDesignerData -> ibisProcessor -> ibisWriter) mirrors the GUI workflow exactly: configure, convert, export. The ibisProcessor call performs the same extraction as the Preview IBIS button, and ibisWriter formats and writes the same IBIS file content as Export IBIS.

Summary

This example demonstrated how to create an IBIS model from SPICE simulation data using the SPICE Simulation workflow in IBIS Designer. The key steps were:

Next steps:

References