Errors in the part properties file.

Syntax errors and omissions in the IBIS files. The report includes the signal name, model name, and number of the pin of the component in the IBIS file, and the IBIS model type for the model in the IBIS file.

Syntax and consistency errors and omissions in the timing file data.

Inconsistencies between IBIS components and timing models data. The report includes information about the pin of the component in the IBIS file, including the signal name, model name, timing model name, number, and I/O type. The report also includes the IBIS model type for the model in the IBIS file.

Parts or pins in parts that are not referenced in the transfer netlist or timing model.

Details on each transfer net such as whether the type of the net is data, clock, or strobe, whether the net is differential or single-ended, and the number of nodes. This report also lists information on the clock, noise, and probe points.

Details on each part.

Lists every signal integrity, HSPICE, and IBIS parameter or extension associated with each model in the design. This includes model name, corner and mode information, waveform DRC and timing extensions among other parameters.

Summary of part transfer nets and timing pin definitions.

Lists the differential pins and components associated with each part.

Summary of all output delays and setup and hold statements in each timing model.

Lists most of the waveform DRC rules and timing levels used by the product. The report includes the actual parameter used (following the precedence rules) and the value assigned to that parameter.

Inconsistencies between transfer nets, IBIS components and timing models. The part, IBIS and timing files listed are not necessarily where the error occurred, but simply a listing of all files involved in the error checking.

Number of errors and warnings found during waveform analysis.

Lists any fatal waveform error found on any edge during waveform processing. Fatal errors are errors that cause the inability to generate any waveform or timing data at all. This tab will only appear if there are fatal violations of the DRC rules.

Lists violations of waveform rules as applied to each edge. The product applies a number of waveform rules to each edge to verify that the transition meets various IC vendor AC specs including edge rate, ringback and monotonic (clock nets). If the transition violates any of these rules, the timing of the transition may be suspect.

Lists violations of these waveform overshoot rules. Overshoot does not affect the signaling operation of an I/O buffer but can affect the lifetime of an IC. Overshoot can occur in two ways: when the waveform instantaneously exceeds absolute overshoot limits set in the IBIS model, and when the waveform exceeds a lesser overshoot voltage limit for more than a prescribed time.

Lists a summary of eye details for each node in each transfer net.

Eye information for each receiver node in each simulation.

Details of slew-rate derating calculations. This tab will be present if one or more models contain slew rate derating tables.

Variables and results from the statistical analysis simulation (STAT mode only).

Variables and results from the time domain analysis simulation (STAT mode only).

Crosstalk and eye heights of the widebus sheets that have been simulated.

Summary of the waveform margins for each transfer net.

Summary of the waveform errors (if any) and waveform DRC margins associated with each simulation.

Summary of the data for each IBIS model used in the simulation. The report includes the measurement thresholds and the parameters that are used for each threshold.

Available when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Available when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Available when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Available in post-layout when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Available when the analysis is defined using TiVW and ViVW (DDR4 and DDR5).

Rolls up the By Variation Details tab by combining all transitions in the same transfer net.

Rolls up the By Variation tab by combining identical transfers (same driver and receiver).

Includes setup margin, hold margin, etch delay, AC noise, transfer net, and extended net details.

Available only in post-layout.

This tab contains two rows for each transfer net in the By Variation Details Summary Tab. One has the smallest setup margin for that transfer net, the other has the smallest hold margin for that transfer net.

Rolls up the By Variation tab by combining identical drivers.

Rolls up the By Variation tab by combining identical receivers.

Contains the setup and hold margin for rising and falling data edges in each simulation.

Contains the setup and hold margin for rising and falling data edges in each simulation.

Lists the skews between the clock pins used in synchronous timing analysis.

Contains the details of source-synchronous constraints that do not have a strobe.

Contains the coupling effects on timing.

Contains the voltage variation on victim nets caused by coupling.

Summarizes each edge in each simulation.

Contains information about nets (transfer and extended), designator, parts, IBIS model, and timing model.

Contains most of the waveform DRC rules and timing levels used by the product. The actual parameter used (following the precedence rules) and the value assigned to that parameter.

Complete netlist with model data for each pin.

List of nets whose connections appear to be incorrect. The tool looks at the logical pin names on all pins connected to a net and looks for inconsistencies that may indicate swapped bits of a bus. For example, if an extended net has a pin with logical name DATA0 on one device and a pin with logical name DATA7 on another device the net will be considered swizzled.

Number of simulation decks generated, errors in their generation and consistency checks.

Data on the Spice decks generated listed by simulation name, including whether models are Spice or IBIS

List of reasons why a Spice deck was not generated.