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Pre-Layout Analysis of Parallel Link Projects
Analyze parallel link projects before designing board layouts
You can run simulations using IBIS-AMI models to determine the system-level noise and timing margins before designing PCB layouts. The pre-layout analysis environment helps you to generate design guidelines for your board layouts, package layouts, connectors, and cabling.
Apps
| Parallel Link Designer | Analyze PCB designs for parallel link applications (Since R2021b) |
| Signal Integrity Viewer | View the signal integrity results of Serial Link Designer or Parallel Link Designer apps (Since R2021b) |
Objects
si.MER | Reconstruct MER waveform and estimate MER statistical eye of nonlinear systems (Since R2024b) |
Topics
- Pre-Layout Analysis of Parallel Link
Learn the basics of pre-layout analysis.
- Customize Parallel Link Project for Pre-Layout Analysis
Edit transmission line models, designators, S-parameters, and IBIS files to customize pre-layout analysis.
- Results of Pre-Layout Analysis in Parallel Link
View, interpret, and debug the pre-layout analysis results.
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