D Flip-Flop
Model a positive-edge-triggered enabled D flip-flop
Libraries:
Simulink Extras / Flip Flops
Description
The D Flip-Flop block models a positive-edge-triggered enabled D flip-flop. The D Flip-Flop block has three inputs:
D — data input
CLK — clock signal
!CLR — enable input signal
On the positive (rising) edge of the clock signal, if the block is enabled (!CLR is greater than zero), the output Q is the same as the input D. The truth table for the D Flip-Flop block follows.
Note
The D Flip-Flop block treats a nonzero input as true
(1
).
D | Q | !Q |
---|---|---|
1 | 1 | 0 |
0 | 0 | 1 |
If the block is not enabled on the rising edge of the clock signal, Q is reset to zero. When the clock signal is not rising, the block remains in the previous state.
Logic Signals as Boolean or Double Data Types
The Implement logic signals as boolean data (vs. double) configuration parameter setting affects the input and output data types of the D Flip-Flop block because the D Flip-Flop is a masked subsystem that uses the Logical Operator block. The Logical Operator block in the masked subsystem has the following parameter settings:
Block Parameter | Setting |
---|---|
Output data type | Inherit: Logical |
Require all inputs and output to have the same data type | On |
For more information about the Implement logic signals as boolean data (vs. double) configuration parameter, see Implement logic signals as Boolean data (vs. double).
Ports
Input
Output
Version History
Introduced in R2008b