Wrap To Zero

Set output to zero if input is above threshold

Libraries:
Simulink / Discontinuities
HDL Coder / Discontinuities

Description

The Wrap To Zero block sets the output to zero when the input is above the Threshold value. When the input is less than or equal to the Threshold, then the output is equal to the input.

Ports

Input

expand all

Port_1 — Input signal
scalar | vector

Input signal, specified as a scalar or vector. Signal values equal to or greater than the value of Threshold are set to zero.

Output

expand all

Port_1 — Output signal
scalar | vector

Output signal set to the input signal value or zero. The data type of the output is the same data type as the input.

Tip

If the input data type cannot represent zero, parameter overflow occurs. To detect this overflow, go to the Diagnostics > Data Validity pane of the Configuration Parameters dialog box and set Parameters > Detect overflow to warning or error.

Parameters

expand all

To edit the parameters for the Wrap to Zero block, double-click the block icon.

Threshold — Threshold for outputting zero
`255` (default) | scalar

Threshold value for setting the output value to zero.

Programmatic Use

Block Parameter: Threshold

Type: character vector

Values: scalar

Default: '255'

Block Characteristics

Data Types	`Boolean` \| `double` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

The input signal and Threshold parameter must have equal size. For example, if the input is a two-dimensional vector, Threshold must also be a two-dimensional vector.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

Wrap To Zero

Description

Ports

Input

Port_1 — Input signal scalar | vector

Output

Port_1 — Output signal scalar | vector

Parameters

Threshold — Threshold for outputting zero 255 (default) | scalar

Programmatic Use

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Port_1 — Input signal
scalar | vector

Port_1 — Output signal
scalar | vector

Threshold — Threshold for outputting zero
`255` (default) | scalar

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.