Support for Fixed Reference Design

Create SoC model for fixed reference design, edit created model to include algorithm, simulate and/or build and deploy model on MPSoC, RFSoC, and Versal^® ACAP devices

This workflow enables algorithm and system designers to generate an HDL IP core and integrate it into a fixed reference design for rapid prototyping. Create an SoC model based on the selected reference design for the supported AMD^® MPSoC, RFSoC, and Versal ACAP devices by using the SoC Model Creator tool. Use the created model as a template to design and simulate your FPGA algorithm and processor algorithm. Then, generate a bitstream and host I/O model, build a software application, and program the board by using the SoC Builder tool.

Topics

Configure Design Using SoC Model Creator
Customize and design an SoC model by using the SoC Model Creator tool.
Generate Design Using SoC Builder
Generate an SoC design and run it on the target hardware board using the SoC Builder tool.
SoC Generation Workflows
Choose between SoC Builder workflow or IP Core Generation workflow for deploying your design on an SoC device.
Reference Design for Zynq-7000 and MPSoC Devices
Learn about how to use Default System with SoC Blockset reference design and its requirements.
Reference Designs for RFSoC Devices
Learn about how to use RFSoC reference designs and their requirements.

Tools

SoC Model Creator

Create SoC model based on selected reference design (Since R2021b)

Objects

soc.RFDataConverter Configure the RF Data Converter on the RFSoC device from MATLAB (Since R2020b)

Featured Examples

Transmit and Receive Tone Using IP Core Generation Workflow on RFSoC Device

Design and implement hardware algorithm using RFSoC support for fixed reference design workflow.

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Transmit Signal Waveform Using DDR4 on AMD RFSoC Device

Design and implement hardware algorithm using RFSoC support for fixed reference design workflow.

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Full Duplex Data Streaming between Software and Hardware on Versal Platform

Deploy system for full duplex data streaming between hardware and software using SoC Blockset™ on Xilinx^® Versal AI Core Series VCK190 Evaluation Kit.

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Multi-Channel Transceiver Using Xilinx RFSoC Device

Implement multi-channel transceiver using RF Data Converter on Xilinx RFSoC device.

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Receive Tone with DDR4 Using IP Core Generation Workflow on Xilinx RFSoC Device

Design, simulate, and deploy algorithm to write and read captured RF samples from external DDR4 memory on Xilinx RFSoC device.

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