Hardware I/O Devices
Model the connection between the IO devices on your board and your FPGA
logic
Use these blocks to create models that simulate the connection between your SoC design and these IO devices.
Blocks
HDMI Rx | Convert video stream to YCbCr 4:2:2 pixel stream |
HDMI Tx | Convert YCbCr 4:2:2 pixel stream to video frame |
AD9361 Rx | Connect hardware logic to AD9361-based Zynq receiver |
AD9361 Tx | Connect hardware logic to AD9361-based Zynq transmitter |
Zynq and FMCOMMS2/3/4 Receiver Configuration | Connect hardware logic to FMCOMMS Zynq radio receiver hardware |
Zynq and FMCOMMS2/3/4 Transmitter Configuration | Connect hardware logic to FMCOMMS Zynq radio transmitter hardware |
ADAU1761 Codec | Connect hardware logic to ADAU1761 signals on hardware board |
RF Data Converter | Provide RF data path interface to hardware logic (Since R2020a) |
ADC To Vector | Convert concatenated 16-bit ADC input samples to vector outputs (Since R2020b) |
Vector To DAC | Convert vector inputs to concatenated 16-bit DAC output samples (Since R2020b) |
RFDC Bus Creator | Convert control signals into RF Data Converter real-time interface-compatible bus (Since R2022a) |
RFDC Bus Selector | Convert RF Data Converter real-time interface-compatible bus into control signals (Since R2022a) |
OTAVA DTRX2 | Integrate OTAVA DTRX2 mmWave radio card with ZCU208 board (Since R2023a) |
Aurora 64B66B | Provide high-speed serial communication using Xilinx Aurora interface (Since R2023a) |
Tools
HDL IP Importer | Import HDL IP core into SoC model (Since R2023a) |
Topics
Wireless Applications
- OFDM Transmit and Receive Using Xilinx RFSoC Device
Simulate and deploy OFDM transmit and receive algorithm using SoC Blockset™ on Xilinx® RFSoC device. - Introduction to 5G NR Signal Detection using Xilinx RFSoC
Deploy primary synchronization signal (PSS) correlation and synchronization signal block (SSB) demodulation using SoC Blockset on Xilinx RFSoC device. - 5G NR SIB1 Recovery for FR1 and FR2 Using Xilinx RFSoC Device
Deploy 5G NR SIB1 recovery algorithm for FR1 and FR2 using SoC Blockset on Xilinx RFSoC device. - 5G NR Downlink Signal Measurements Using Xilinx RFSoC Device
Measure SSB signal quality and error vector magnitude (EVM) of the received resource grid using SoC Blockset on Xilinx RFSoC device. - DVB-S2 HDL PL Header Recovery Using Analog Devices AD9361/AD9364
Deploy Digital Video Broadcasting Satellite Second Generation (DVB-S2) time, frequency, and phase synchronization and PL header recovery algorithm using SoC Blockset. - DVB-S2 Receive Using Xilinx RFSoC Device
Simulate and deploy DVB-S2 transmit and receive algorithm using SoC Blockset on Xilinx RFSoC device. - WLAN Receiver Using Xilinx RFSoC Device
Simulate and deploy WLAN transmit and receive algorithm using SoC Blockset on Xilinx RFSoC device. - Pulse-Doppler Radar Using Xilinx RFSoC Device
Build, simulate, and deploy pulse-Doppler radar system using SoC Blockset on Xilinx RFSoC device.
Video Applications
- Edge Detection and Image Overlay
Implement an edge detection and image overlay system with HDMI input and output. - Vertical Video Flipping Using External Memory
Flip an incoming video stream vertically by using a random-access external memory interface. - Contrast Limited Adaptive Histogram Equalization with External Memory
This example shows how to implement the contrast-limited adaptive histogram equalization (CLAHE) algorithm for FPGA, including an external memory interface.