Overview of Time-Base Synchronization in ePWM Type 4

Time-Base Clock Synchronization

The TBCLKSYNC bit in the peripheral clock enable registers allows all users to globally synchronize all enabled ePWM modules to the time-base clock (TBCLK). When set, all enabled ePWM module clocks are started with the first rising edge of TBCLK aligned. This is done by default for the ePWM blocks.

Time-Base Counter Peripheral Synchronization

Each ePWM module has a peripheral synchronization output (SYNCPER). This output signal is used to synchronize the CMPSS to the EPWM.

The source of this signal can be configured in the ePWM block as shown below:

The corresponding signal can be used with CMPSS using the EPWM peripheral synchronization event parameter under Hardware Implementation > Target hardware resources > CMPSS.

Time-Base Counter Synchronization

Time-base counter synchronization allows for increased flexibility of synchronization of the ePWM modules. The clock synchronization scheme allows ePWM modules to operate as a single system when required. Additionally, this synchronization scheme can be extended to the capture peripheral submodules (eCAP). In Type 4 ePWM, there are two types of time-base counter synchronization scheme available.

Time base counter synchronization options in ePWM

In processors F2837x, F2807x and F28004x, the ePWM modules are chained together as shown below.

In processors F2838x, F28002x and F28003x, there is no fixed chain of synchronization signals but each ePWM or eCAP module can be configured to use or ignore the synchronization input and can be the source of synchronization signal i.e. any ePWM or eCAP can be synchronized with any other ePWM or eCAP.

When the PHSEN bit in TBCTL is set the time-base counter (TBCTR) of the ePWM module is automatically loaded with the phase register (TBPHS) contents when one of the following conditions occur:

EPWMxSYNCI/Synchronization Input Pulse - The value of the phase register is loaded into the counter register when an input synchronization pulse is detected (TBPHS → TBCTR). This operation occurs on the next valid time-base clock (TBCLK) edge.
Software Forced Synchronization Pulse - Writing a 1 to the SWFSYNC control bit in TBCTL invokes a software forced synchronization. This pulse is ORed with the synchronization input signal, and therefore has the same effect as a pulse on EPWMxSYNCI.
Digital Compare Event Synchronization Pulse - DCAEVT1 and DCBEVT1 digital compare events can be configured to generate synchronization pulses which have the same effect as EPWMxSYNCI.
In up-down-count mode, the PSHDIR bit in TBCTL register configures the direction of the time-base counter immediately after a synchronization event. The new direction is independent of the direction prior to the synchronization event. The PHSDIR bit is ignored in count-up or count-down modes.

These options are set in ePWM block as shown below.

The source for EXTSYNCOUT and the EPWMSYNCI signal can be selected under Hardware Implementation > Target hardware resources > ePWM as shown.

Note

EXTSYNCOUT and EPWMSYNCI parameters vary based on the processor.
For processors F28004x/F2837xD/F2837xS/F2807x, EXTSYNCIN1 and EXTSYNCIN2 are mapped to Input X-BAR 5 and Input X-BAR 6 respectively.
For processors F2838x/F28003x/F28002x, EXTSYNCOUT option can be used to send synchronization output from eCAP in a model without ePWM blocks.

EPWMxSYNCO signal is the output pulse is used to synchronize the counter of other ePWM modules. For processors F2837x/F2807x and F28004x, EPWMxSYNCO signal can be generated as shown in the diagram below.

For processors F2838x, F28002x and F28003x, EPWMxSYNCO signal can be generated under multiple conditions as shown below.

Note

Configuration of one-shot sync mode is currently not supported.

EPWMxSYNCO can be configured in the ePWM block as shown below.

For F2837x/07x/004x processors.

For F2838x/002x and 003x processors.

Time base counter synchronization options in eCAP

eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come from eCAP, X-Bar or EPWM.

SYNCOUT signal from eCAP can be passed through or generated when CTR=PRD.

Although synchronization is possible in both eCAP as well as APWM mode for eCAP, CTR=PRD source for SYNCOUT signal is valid only in case of eCAP in APWM mode.

The phase offset, software sync-in and the syncout option can be selected in eCAP block as shown below.

The eCAP SYNCIN signal can be selected from the eCAP tab in configuration parameter. Ensure that the Enable counter Sync-In mode is enabled in the eCAP block for synchronization input to have effect.