LDPC Decoder

Decode quasi-cyclic low-density parity-check code

Since R2023b

Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The LDPC Decoder block implements a quasi-cyclic low-density parity-check (QC-LDPC) decoder with hardware-friendly control signals. The block accepts log-likelihood ratio (LLR) values and a stream of control signals and outputs decoded bits, a stream of control signals, and a signal that indicates whether the block is ready to accept new inputs.

This block provides an option to implement layered belief propagation with either the normalized min-sum approximation algorithm or the min-sum approximation algorithm. The LDPC Decoder block supports scalar and N-element column vector inputs with a specified parity-check matrix and block size. The block supports the early termination feature to help improve decoding performance and faster convergence speeds at high signal noise ratio (SNR) conditions. The block supports QC-LDPC codes of circulant weight 1.

The block enables decoding of multiple code rates to help achieve high throughput efficiency with a high degree of code rate flexibility. You can use this block to develop a standard-based or generalized receiver that uses a QC-LDPC for forward error correction (FEC) coding. The block provides an architecture suitable for HDL code generation and hardware deployment. For more information, see Algorithms.

Examples

LDPC Encode and Decode of Streaming Data

Use LDPC Encoder and LDPC Decoder blocks and verify their functionality.

Open Script

Ports

Input

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data — Input LLR values
scalar | column vector

Input log-likelihood ratio (LLR) values, specified as a scalar or a column vector of size n, where n must be factor of Block size.

The data type of this input must be a signed fixed-point with a word length in the range [4, 16 ] and fraction length in the range [0, 15 ].

Data Types: int8 | int16 | fixed point

ctrl — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the input frame
end — Indicates the end of the input frame
valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

iter — Number of iterations
scalar

Number of iterations, specified as a integer in the range [1, 63].

If you specify iter as a value greater than 63, the block automatically sets the iter value to 8 and performs the decoding operation.

Dependencies

To enable this port, set the Source for number of iterations parameter to Input port.

Data Types: uint8

Output

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data — Decoded data bits
scalar | column vector

Decoded output data bits, returned as a scalar or a column vector of size n.

Data Types: Boolean

ctrl — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the output frame
end — Indicates the end of the output frame
valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

actIter — Actual number of iterations
scalar

Actual number of iterations the block takes to decode the output, returned as a scalar.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Early.

Data Types: uint8

parityCheck — Parity check status indicator
scalar

Parity check status indicator, returned as a Boolean scalar. The port indicates the status of the parity check after the decoding operation.

0 — Indicates that the parity check failed
1 — Indicates that the parity check passed

Dependencies

To enable this port, select the Enable parity check output port parameter.

Data Types: Boolean

nextFrame — Ready for new inputs
scalar

The block sets this signal to 1 when the block is ready to accept the start of the next frame. If the block receives an input start signal while nextFrame is 0, the block discards the frame in progress and begins processing the new data.

For more information, see Using the nextFrame Output Signal.

Data Types: Boolean

Parameters

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Parity-check matrix — QC-LDPC matrix
`[5 14 12 1 2 37 45 26 24 0 3 -1 34 7 46 10 -1 -1 -1 -1; 0 35 1 26 0 10 16 16 34 4 2 23 0 51 -1 49 20 -1 -1 -1; 12 28 22 46 3 16 51 2 25 29 19 18 52 -1 37 -1 34 39 -1 -1; 0 51 16 31 13 39 27 33 8 27 53 13 -1 52 33 -1 -1 38 7 -1; 36 6 3 51 4 19 4 45 48 9 -1 11 22 23 43 -1 -1 -1 14 1]` (default) | any QC-LDPC matrix with circulant weight 1

Specify a QC-LDPC parity-check matrix of size M-by-N, where M is the number of rows in the parity-check matrix and N is the number of columns in the parity-check matrix. N must be in the range [4, 128]. M must be less than N and must be in the range [3, N–1]. The last M columns of the parity-check matrix must be invertible in GF(2).

To learn more about the supported parity-check matrices, see Parity-Check Matrix.

Block size — Size of block
`56` (default) | integer in the range [2, 512]

Specify the block size. The block size must be an integer in the range [2, 512].

Algorithm — Type of algorithm
`Min-sum` (default) | `Normalized min-sum`

Select the type of LDPC decoding algorithm. For more information, see Algorithms.

Min-sum — Use this option to select the layered belief propagation algorithm with a min-sum approximation. For more information, see Min-Sum Approximation.
Normalized min-sum — Use this option to select the layered belief propagation algorithm with a normalized min-sum approximation. For more information, see Normalized Min-Sum Approximation.

Scaling factor — Scaling factor
`0.75` (default) | values in the range from 0.5 to 1, incremented by 0.0625

Specify the scaling factor.

Dependencies

To enable this parameter, set the Algorithm parameter to Normalized min-sum.

Decoding termination criteria — Termination criteria
`Max` (default) | `Early`

Select the decoding termination criteria.

Max — Terminates decoding when the block reaches the number of iterations specified through the Number of iterations parameter or through the iter input port.
Early — Terminates decoding when all of the parity checks are met or when the block reaches the maximum number of iterations specified through the Maximum number of iterations parameter or through the iter input port.

Source for number of iterations — Source selection for number of iterations
`Property` (default) | `Input port`

Select the source for specifying the number of iterations.

You can set the number of iterations by using either an input port or a parameter.

Select Property to enable either the Number of iterations parameter or the Maximum number of iterations parameter.
Select Input port to enable the iter port.

Number of iterations — Number of iterations
`8` (default) | integer in the range [1, 63]

Specify the number of iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Max and the Source for number of iterations parameter to Property.

Maximum number of iterations — Maximum number of iterations
`8` (default) | integer in the range [1, 63]

Specify the maximum number of iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Early and the Source for number of iterations parameter to Property.

Enable parity check output port — Parity check status
`off` (default) | `on`

Select this parameter to enable the parityCheck output port to view the status of the parity check.

More About

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Parity-Check Matrix

QC-LDPC codes are an important class of codes within the family of LDPC codes. You can use LDPC codes in many applications because of their simple encoding implementation of using cyclic shift registers. The LDPC Encoder block performs encoding using a parity-check matrix.

The block supports matrices with a circulant weight of 1. Each element in the parity-check matrix corresponds to a submatrix of size Z. The elements in the parity-check matrix must be in the range [–1, Z –1], where Z is the block size. In a parity-check matrix, –1 corresponds to a zero submatrix, 0 corresponds to an identity submatrix, 1 corresponds to an identity submatrix circularly shifted by one time, and n corresponds a submatrix circularly shifted by n times, where n is any value in the range [0, Z – 1].

This figure shows a parity-check matrix of size 2-by-4 whose block size is 4.

In this parity-check matrix:

–1 represents a zero submatrix, [0 0 0 0; 0 0 0 0; 0 0 0 0; 0 0 0 0].
0 represents an identity submatrix, [1 0 0 0; 0 1 0 0; 0 0 1 0; 0 0 0 1].
1 represents an identity submatrix circularly shifted by one time, [0 1 0 0; 0 0 1 0; 0 0 0 1;1 0 0 0].
2 represents an identity submatrix circularly shifted by two times, [0 0 1 0; 0 0 0 1; 1 0 0 0; 0 1 0 0].
3 represents an identity submatrix circularly shifted by three times, [0 0 0 1; 1 0 0 0; 0 1 0 0; 0 0 1 0].

Algorithms

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This figure shows the architecture block diagram of the LDPC Decoder block. The Controller block controls the layer and iteration count of the decoding process. The Variable node RAM block stores the variable node (VN) messages, and Check node RAM block stores the check node messages (CN). The Functional Unit block calculates the variable node (VN) messages and check node (CN) messages based on the layered belief propagation and either the normalized min-sum approximation algorithm or the min-sum approximation algorithm. The Termination/Parity check status block calculates the parity checks and provides the parity check status after each iteration.

LDPC Block Architecture

The implementation of the block matches the performance of the function ldpcDecode.

This plot shows the performance of block with a parity check matrix specified for a 4-bit LLR input with a block length of 1120 in Docsis 3.1 standard, and when the Algorithm parameter is set to Min-sum.

LDPC Decoder BER Performance Comparison Min-sum for Docsis 3.1 standard

This plot shows the performance of block with a parity check matrix specified for a 4-bit LLR input with bgn 1 and lifting size 384 in 5G NR standard, and when the Algorithm parameter is set to Min-sum.

LDPC Decoder BER Performance Comparison Min-sum 5G NR standard

Belief Propagation Decoding

The implementation of the belief propagation algorithm is based on the decoding algorithm presented in [1]. For a transmitted LDPC-encoded codeword, c, where $c = (c_{0}, c_{1}, ..., c_{n - 1})$ , the input to the LDPC decoder is the log-likelihood ratio (LLR) value $L (c_{i}) = \log (\frac{\Pr (c_{i} = 0 | channel output for c_{i})}{\Pr (c_{i} = 1 | channel output for c_{i})})$ .

In each iteration, the key components of the algorithm are updated based on these equations:

$L (r_{j i}) = 2 atanh (\prod_{i^{'} \in V_{j} \ i} \tanh (\frac{1}{2} L (q_{i^{'} j})))$ ,

$L (q_{i j}) = L (c_{i}) + \sum_{j^{'} \in C_{i} \ j} L (r_{j^{'} i})$ , initialized as $L (q_{i j}) = L (c_{i})$ before the first iteration, and

$L (Q_{i}) = L (c_{i}) + \sum_{j^{'} \in C_{i}} L (r_{j^{'} i})$ .

At the end of each iteration, $L (Q_{i})$ is an updated estimate of the LLR value for the transmitted bit $c_{i}$ . The value $L (Q_{i})$ is the soft-decision output for $c_{i}$ . If $L (Q_{i}) < 0$ , the hard-decision output for $c_{i}$ is 1. Otherwise, the output is 0.

Layered Belief Propagation Decoding

The implementation of the layered belief propagation algorithm is based on the decoding algorithm presented in [2], Section II.A. The decoding loop iterates over subsets of rows (layers) of the PCM. For each row, m, in a layer and each bit index, j, the implementation updates the key components of the algorithm based on these equations:

(1) $L (q_{m j}) = L (q_{j}) - R_{m j}$ ,

(2) $A_{m j} = \sum_{\begin{matrix} n \in N (m) \\ n \neq j \end{matrix}} ψ (L (q_{m n}))$ ,

(3) $s_{m j} = \prod_{\begin{matrix} n \in N (m) \\ n \neq j \end{matrix}} sign (L (q_{m n}))$ ,

(4) $R_{m j} = - s_{m j} ψ (A_{m j})$ , and

(5) $L (q_{j}) = L (q_{m j}) + R_{m j}$ .

For each layer, the decoding equation (5) works on the combined input obtained from the current LLR inputs $L (q_{m j})$ and the previous layer updates $R_{m j}$ .

Because only a subset of the nodes is updated in a layer, the layered belief propagation algorithm is faster compared to the belief propagation algorithm. To achieve the same error rate as attained with belief propagation decoding, use half the number of decoding iterations when using the layered belief propagation algorithm.

Min-Sum Approximation

The implementation of the min-sum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by

$A_{m j} = \min_{\begin{matrix} n \in N (m) \\ n \neq j \end{matrix}} (| L (q_{m n}) | \cdot α)$ ,

where α is 1.

Normalized Min-Sum Approximation

The implementation of the normalized min-sum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by

$A_{m j} = \min_{\begin{matrix} n \in N (m) \\ n \neq j \end{matrix}} (| L (q_{m n}) | \cdot α)$ ,

where α is in the range [0, 1] and is the scaling factor specified by the Scaling factor parameter. This equation is an adaptation of equation (4) presented in [3].

Latency

The latency of the block varies with the Parity-check matrix parameter and the number of iterations. Because the latency varies, use the nextFrame control signal output port to determine when the block is ready for a new input frame.

The latency of the block is equal to r x (t + m x 10) + (inputLen/vecSize) + 13. In this calculation, r is the number of iterations, t is twice the total number of non –1 elements in the parity check matrix, m is the number of rows in the parity check matrix, inputLen is the input length, and vecSize is the input vector size.

This figure shows a sample output and latency of the LDPC Decoder block for a scalar input when you use default settings for the block parameters. The latency of the block is 2796 clock cycles.

This figure shows a sample output and latency of the LDPC Decoder block for a 8-by-1 vector input when you use default settings for the block parameters. The latency of the block is 1816 clock cycles.

Throughput

The throughput of the block is calculated as (cwLen / latency) x f_max. In this calculation, cwLen is the code word length, f_maxis the maximum operating frequency of the block, and latency is the latency of the block.

For more information about the latency calculation, see Latency. For more information about the maximum operating frequency, see Performance.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. It also varies based on the type of input, type of algorithm, and the word length of the input LLR values.

This table shows the resource and performance data synthesis results of the block, when you use default settings for the block parameters and specify scalar and 56-by-1 vector type input LLR values of data type fixdt(1,4,0). The generated HDL is targeted to the AMD^® Zynq^® UltraScale+™ MPSoC evaluation board.

Input Data	Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
Scalar	8670	5533	28	464.04
Vector 56-by-1	8469	6261	28	455.80

References

[1] Gallager, R. “Low-Density Parity-Check Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. https://doi.org/10.1109/TIT.1962.1057683.

[2] Hocevar, D.E. “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes.” In IEEE Workshop On Signal Processing Systems, 2004. SIPS 2004, 107–12. Austin, Texas, USA: IEEE, 2004. https://doi.org/10.1109/SIPS.2004.1363033.

[3] Chen, Jinghu, R.M. Tanner, C. Jones, and Yan Li. "Improved Min-Sum Decoding Algorithms for Irregular LDPC Codes." In Proceedings. International Symposium on Information Theory, 2005. ISIT 2005. https://doi: 10.1109/ISIT.2005.1523374.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2023b

LDPC Decoder

Description

Examples

LDPC Encode and Decode of Streaming Data

Ports

Input

data — Input LLR values scalar | column vector

ctrl — Control signals accompanying sample stream samplecontrol bus

iter — Number of iterations scalar

Dependencies

Output

data — Decoded data bits scalar | column vector

ctrl — Control signals accompanying sample stream samplecontrol bus

actIter — Actual number of iterations scalar

Dependencies

parityCheck — Parity check status indicator scalar

Dependencies

nextFrame — Ready for new inputs scalar

Parameters

Block size — Size of block 56 (default) | integer in the range [2, 512]

Algorithm — Type of algorithm Min-sum (default) | Normalized min-sum

Scaling factor — Scaling factor 0.75 (default) | values in the range from 0.5 to 1, incremented by 0.0625

Dependencies

Decoding termination criteria — Termination criteria Max (default) | Early

Source for number of iterations — Source selection for number of iterations Property (default) | Input port

Number of iterations — Number of iterations 8 (default) | integer in the range [1, 63]

Dependencies

Maximum number of iterations — Maximum number of iterations 8 (default) | integer in the range [1, 63]

Dependencies

Enable parity check output port — Parity check status off (default) | on

More About

Parity-Check Matrix

Algorithms

Belief Propagation Decoding

Layered Belief Propagation Decoding

Min-Sum Approximation

Normalized Min-Sum Approximation

Latency

Throughput

Performance

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Functions

Blocks

data — Input LLR values
scalar | column vector

ctrl — Control signals accompanying sample stream
`samplecontrol` bus

iter — Number of iterations
scalar

data — Decoded data bits
scalar | column vector

ctrl — Control signals accompanying sample stream
`samplecontrol` bus

actIter — Actual number of iterations
scalar

parityCheck — Parity check status indicator
scalar

nextFrame — Ready for new inputs
scalar

Block size — Size of block
`56` (default) | integer in the range [2, 512]

Algorithm — Type of algorithm
`Min-sum` (default) | `Normalized min-sum`

Scaling factor — Scaling factor
`0.75` (default) | values in the range from 0.5 to 1, incremented by 0.0625

Decoding termination criteria — Termination criteria
`Max` (default) | `Early`

Source for number of iterations — Source selection for number of iterations
`Property` (default) | `Input port`

Number of iterations — Number of iterations
`8` (default) | integer in the range [1, 63]

Maximum number of iterations — Maximum number of iterations
`8` (default) | integer in the range [1, 63]

Enable parity check output port — Parity check status
`off` (default) | `on`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.