LDPC Encoder

Encode quasi-cyclic low-density parity-check code

Since R2023a

Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The LDPC Encoder block implements a quasi-cyclic low-density parity-check (QC-LDPC) encoder with hardware-friendly control signals. The block accepts data bits and a stream of control signals and outputs encoded bits, a stream of control signals, and a signal that indicates whether the block is ready to accept new inputs.

The block supports scalar inputs with a specified parity-check matrix and block size. The block also supports lower-triangular or upper-triangular, dual-diagonal, and mixed-diagonal parity-check matrices. The block supports LDPC codes of circulant weight 1. For more information, see Parity-Check Matrix.

You can use this block to develop a standard-based or generalized transmitter that uses a QC-LDPC for forward error correction (FEC) coding. The block provides an architecture suitable for HDL code generation and hardware deployment. See Algorithms.

Examples

Encode Data with Quasi-Cyclic Low Density Parity Check Code

Encode data bits with quasi-cyclic low-density parity-check codes.

Open Script

LDPC Encode and Decode of Streaming Data

Use LDPC Encoder and LDPC Decoder blocks and verify their functionality.

Open Script

Ports

Input

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data — Data bits
scalar

Data bits, specified as a scalar. The input data length must be (N–M) x Z, where M is the number of rows in the parity-check matrix, N is the number of columns in the parity-check matrix, and Z is the block size.

Data Types: Boolean

ctrl — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the input frame
end — Indicates the end of the input frame
valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Output

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data — Encoded data bits
scalar

Encoded data bits, returned as a scalar.

Data Types: Boolean

ctrl — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the output frame
end — Indicates the end of the output frame
valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

nextFrame — Ready for new inputs
scalar

The block sets this signal to 1 when the block is ready to accept the start of the next frame. If the block receives an input start signal while nextFrame is 0, the block discards the frame in progress and begins processing the new data.

For more information, see Using the nextFrame Output Signal.

Data Types: Boolean

Parameters

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Parity-check matrix — QC-LDPC matrix
`[5 14 12 1 2 37 45 26 24 0 3 -1 34 7 46 10 -1 -1 -1 -1; 0 35 1 26 0 10 16 16 34 4 2 23 0 51 -1 49 20 -1 -1 -1; 12 28 22 46 3 16 51 2 25 29 19 18 52 -1 37 -1 34 39 -1 -1; 0 51 16 31 13 39 27 33 8 27 53 13 -1 52 33 -1 -1 38 7 -1; 36 6 3 51 4 19 4 45 48 9 -1 11 22 23 43 -1 -1 -1 14 1]` (default) | any QC-LDPC matrix with circulant weight 1

Specify a QC-LDPC parity-check matrix of size M-by-N, where M is the number of rows in the parity-check matrix and N is the number of columns in the parity-check matrix. N must be in the range [4, 128]. M must be less than N and must be in the range [3, N–1]. The last M columns of the parity-check matrix must be invertible in GF(2).

To learn more about the supported parity-check matrices, see Parity-Check Matrix.

Block size — Size of block
`56` (default) | integer in the range [2, 512]

Specify the block size. The block size must be an integer in the range [2, 512].

More About

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Parity-Check Matrix

QC-LDPC codes are an important class of codes within the family of LDPC codes. You can use LDPC codes in many applications because of their simple encoding implementation of using cyclic shift registers. The LDPC Encoder block performs encoding using a parity-check matrix.

The block supports matrices with a circulant weight of 1. Each element in the parity-check matrix corresponds to a submatrix of size Z. The elements in the parity-check matrix must be in the range [–1, Z –1], where Z is the block size. In a parity-check matrix, –1 corresponds to a zero submatrix, 0 corresponds to an identity submatrix, 1 corresponds to an identity submatrix circularly shifted by one time, and n corresponds a submatrix circularly shifted by n times, where n is any value in the range [0, Z – 1].

This figure shows a parity-check matrix of size 2-by-4 whose block size is 4.

In this parity-check matrix:

–1 represents a zero submatrix, [0 0 0 0; 0 0 0 0; 0 0 0 0; 0 0 0 0].
0 represents an identity submatrix, [1 0 0 0; 0 1 0 0; 0 0 1 0; 0 0 0 1].
1 represents an identity submatrix circularly shifted by one time, [0 1 0 0; 0 0 1 0; 0 0 0 1;1 0 0 0].
2 represents an identity submatrix circularly shifted by two times, [0 0 1 0; 0 0 0 1; 1 0 0 0; 0 1 0 0].
3 represents an identity submatrix circularly shifted by three times, [0 0 0 1; 1 0 0 0; 0 1 0 0; 0 0 1 0].

The parity-check matrix, H can be partitioned into two sub-matrices H₁ and H₂.

H = [H₁ H₂], where H₁ is the information part of size M x (N – M) and H₂ is the parity part of size M-by-M.

For example, in a parity-check matrix of size 5-by-12, the 5-by-7 submatrix H₁ comprises the information part and the 5-by-5 submatrix H₂ comprises the parity part, as this figure shows.

The LDPC Encoder block supports these types of parity-check matrix.

Lower-triangular — Contains –1s in the upper triangle of the parity part. These matrices are used in the IEEE 802.11ad and DOCSIS 3.1 cable communication standards.
Double-diagonal — Contains three nonzero elements in the first column of the parity part. Also, when you expand each element with an identity matrix of the block size, the sum over (GF2) of these elements must be an identity matrix, which means that at least two elements are the same. The remaining columns of the parity part must contain a bidiagonal pattern with 0s in its diagonals, and –1s in the rest of the parity part. These matrices are used in the Wi-Fi^®, worldwide interoperability for microwave access (WiMAX), and wireless regional area network (WRAN) codes communication standards.
Mix of double-diagonal followed by a single-diagonal lower triangular — Contains a double-diagonal matrix with the extended rows and columns as a lower triangular part with 0s on the diagonals, and –1s in the rest of the parity part. These matrices are used in the 5G NR communication standard.
Upper-triangular — Contains –1s in the lower triangle of the parity part. These matrices are used in custom communications.

Algorithms

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This figure shows the architecture block diagram of the LDPC Encoder block.

The Input Controller block reads and writes input data to the Input RAM block and enables the encoding after writing the entire frame to input RAM. The Parity-check matrix block consists of specified parity-check matrix values and provides shift values to the Shifter block. The Alpha RAM block stores the shifted output. The Parity Controller block calculates parity bit sequences and stores them in the Parity RAM block. The Mux block multiplexes and serializes the bits from the Input RAM and Parity RAM blocks.

LDPC Encoder Block Architecture

Latency

The latency of the block varies with the Parity-check matrix parameter. Because the latency varies, use the nextFrame control signal output port to determine when the block is ready for a new input frame.

This figure shows a sample output and latency of the LDPC Encoder block when you use default settings for the block parameters. The latency of the block is 963 clock cycles.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. Performance also varies with the parity-check matrix and block size.

This table shows the resource and performance data synthesis results of the block with the default parameter configuration. The generated HDL is targeted to the AMD^® Zynq^®- 7000 ZC706 evaluation board.

Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
1608	1416	0	380.42

This table shows the resource and performance data synthesis results of the block when you specify a dual-diagonal parity-check matrix of size 20-by-40 in the Parity-check matrix parameter and set the Block size parameter to 128. The generated HDL targets to the AMD Zynq- 7000 ZC706 evaluation board.

Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
2453	2682	1	300

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2023a

LDPC Encoder

Description

Examples