WGN Generator

Generate white Gaussian noise samples

Since R2026a

Libraries:
Wireless HDL Toolbox / Utilities

Description

The WGN Generator block generates white Gaussian noise (WGN) samples. The block accepts a control to generate WGN samples, and outputs WGN samples and a control signal to indicate a valid noise output. The WGN samples are a sequence of random samples that have a Gaussian distribution with zero mean and specified noise variance. These samples are called white noise because they have the same amount of power at all frequencies. In simple terms, each sample is completely random and does not depend on any other sample.

You can use this block in the design, testing, and validation of communication systems and signal processing applications. The block interface and architecture are suitable for HDL code generation and hardware deployment.

Examples

New

Estimate BER for 64-QAM Signal Using WGN Generator

Use WGN Generator block to estimate BER for 64-QAM signal.

Since R2026a
Open Script

HDL Implementation of AWGN Generator

Implement AWGN generator that is optimized for HDL code generation and hardware implementation.

Open Script

Ports

Input

expand all

valid — Signal to enable WGN generation
scalar

Signal to enable WGN generation, specified as a Boolean scalar. When you set this port to 1 (true), the block generates WGN samples. When you specify 1 (true), the block generates WGN samples.

Data Types: Boolean

reset — Signal to clear internal states
scalar

Signal to clear internal states, specified as a Boolean scalar. When this value is 1 (true), the block stops the current calculation and clears all internal states.

Dependencies

To enable this port, select the Enable reset input port parameter.

Data Types: Boolean

Output

expand all

noise — WGN samples
real scalar | complex scalar

WGN samples, returned as a real or complex scalar. The type of output signal returned at this port depends on the value of the Output signal type parameter.

You can specify the data type for the noise output by using the Output parameter under the Data Types tab.

Data Types: fixed point

valid — Signal to indicate valid noise output
scalar

This port outputs a control signal, returned as a Boolean scalar, to indicate if the output noise is valid.

Data Types: Boolean

Parameters

expand all

Main

Noise variance — Noise variance
`1` (default) | nonnegative scalar

Specify the noise variance as a nonnegative scalar.

Initial seed — Initial seed
`67` (default) | positive scalar up to 2³² – 1

Specify the initial seed value for generating the random number. This value must be a positive scalar up to (2³² – 1).

Output signal type — Type of output noise signal
`Complex` (default) | `Real`

Set the type of the output noise signal as Complex or Real.

Enable reset input port — Option to reset signal
`off` (default) | `on`

Select this parameter to enable the reset input port.

Data Types

Output — Data type of output
`fixdt(1,16,13)` (default) | `fixdt(1,16,0)` | `<data type expression>`

Use this parameter to set the data type of the output.

Algorithms

expand all

The WGN Generator block uses the Box–Muller method to produce Gaussian noise with unit variance. It generates pairs of independent, standard normally distributed random numbers (mean 0, variance 1) from uniformly distributed inputs. To efficiently create these uniform random variables, the block uses the Tausworthe algorithm, which offers both speed and low memory usage. The block then applies logarithmic, square‑root, sine, and cosine operations to transform the uniform values into Gaussian samples. Finally, the block scales the unit‑variance outputs to achieve the desired noise variance. For more information on the Box–Muller method, see [1]

Latency

The block outputs the samples at valid cycles. The latency of the block varies based on the output data type you specify in the Output signal type parameter.

This figure shows a sample output and latency of the WGN Generator block when you set the Noise variance parameter to 1.67, the Seed parameter to 67, and the Output signal type parameter to Complex. The latency of the block is 60 clock cycles, as shown in the following figure.

Performance

The performance of the synthesized HDL code varies based on your target and synthesis options. It also varies based on the output data type.

This table shows the resource and performance data synthesis results of the block with default configuration. The generated HDL is targeted to the AMD^® Zynq^®- 7000 ZC706 Evaluation Board. The design achieves a clock frequency of 281.61 MHz.

Slice LUTs	Slice Registers	DSPs	Block RAMs
3503	3497	4	9.5

References

[1] "J.D. Lee, J.D. Villasenor, W. Luk, and P.H.W. Leong. “A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis,” 659–71. IEEE, 2006. https://doi.org/10.1109/TC.2006.81.

Extended Capabilities

expand all

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

Restrictions

You cannot generate HDL code for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2026a

WGN Generator

Description

Examples

Estimate BER for 64-QAM Signal Using WGN Generator

HDL Implementation of AWGN Generator

Ports

Input

valid — Signal to enable WGN generation scalar

reset — Signal to clear internal states scalar

Dependencies

Output

noise — WGN samples real scalar | complex scalar

valid — Signal to indicate valid noise output scalar

Parameters

Main

Noise variance — Noise variance 1 (default) | nonnegative scalar

Initial seed — Initial seed 67 (default) | positive scalar up to 232 – 1

Output signal type — Type of output noise signal Complex (default) | Real

Enable reset input port — Option to reset signal off (default) | on

Data Types

Output — Data type of output fixdt(1,16,13) (default) | fixdt(1,16,0) | <data type expression>

Algorithms

Latency

Performance

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

valid — Signal to enable WGN generation
scalar

reset — Signal to clear internal states
scalar

noise — WGN samples
real scalar | complex scalar

valid — Signal to indicate valid noise output
scalar

Noise variance — Noise variance
`1` (default) | nonnegative scalar

Initial seed — Initial seed
`67` (default) | positive scalar up to 2³² – 1

Output signal type — Type of output noise signal
`Complex` (default) | `Real`

Enable reset input port — Option to reset signal
`off` (default) | `on`

Output — Data type of output
`fixdt(1,16,13)` (default) | `fixdt(1,16,0)` | `<data type expression>`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.