Hardware Accelerators for NR SIB1 Recovery

Introduction

The Simulink® models described in this example are fixed-point HDL optimized implementations of hardware accelerators for SIB1 recovery for 5G NR. The example details three individual hardware accelerators that perform:

The SIB1 grid recovery algorithm is designed and optimized for frequency range 1 (FR1). The CORESET0 and SIB1 LDPC decoding algorithms support both frequency ranges. The NR HDL SIB1 Recovery example shows how to integrate hardware accelerators with SSB detection and decoding designs to implement a complete SIB1 recovery model. A design supporting both FR1 and FR2 is implemented in the NR HDL SIB1 Recovery for FR2 example.

This example is one of a related set, for more information see NR HDL Reference Applications Overview.

File Structure

This example uses these files.

Simulink models

Simulink data dictionary

MATLAB code

NR HDL SIB1 Demodulation

This figure shows the nrhdlSIB1Demodulation model. The top level of the model reads the signals from the MATLAB base workspace, passes them to the SIB1 Demodulation subsystem, and writes the outputs back to the workspace.

SIB1 Demodulation Subsystem

The SIB1 Demodulation subsystem references the nrhdlDDCFR1Core and nrhdlSIB1DemodulationFR1Core models. The algorithm of the nrhdlSIB1DemodulationFR1Core model is described in the next section. For details about the nrhdlDDCFR1Core model see the NR HDL Cell Search example. The output of the DDC is the input to the SIB1 Demodulation algorithm. The frequency offset applied to the DDC combines the SSB frequency offset estimation term, from a successful MIB recovery, with the SSB to SIB1 offset. The combined frequency offset centers CORESET0 in the received waveform.

Inputs

gridDemodParamBus

Outputs

coreset0ResourcesBus

coreset0OccasionBus

MIBBus

Status Signal States

SIB1 Demodulation Model

This diagram shows the top level of the nrhdlSIB1DemodulationFR1Core model. The design operates on IQ data at 61.44 MHz sample rate and requires parameters from a successful MIB recovery. The start signal begins a SIB1 demodulation operation, set this signal to 1 when all input ports on the paramsIn bus are valid. You must hold the values on paramsIn constant for the duration of the demodulation.

When the OFDM Demod subsystem receives a start signal, it OFDM demodulates the input data and outputs the SIB1 grid. The subsystem computes a variable size FFT, with configurable cyclic prefix length and number of guard subcarriers. The FFT size is selected depending on the subcarrier spacing of the SIB1 grid. For SCS 15 a 2048-point FFT is used, and for SCS 30 a 1024-point FFT is used. These values correspond to the sample rate of 30.72 MHz. The cyclic prefix length varies during OFDM demodulation of the SIB1 grid to account for the longer cyclic prefix symbols present at the halfsubframe boundaries. The number of guard subcarriers is used to extract the SIB1 grid from the full demodulation bandwidth.

The OFDM Demod subsystem requires configuration values to successfully demodulate the SIB1 grid. These values are computed from the results of MIB recovery. The Configuration subsystem constructs the MIB from the PBCH payload and parses the pdcchSIB1Config field to determine coreset0Resources and coreset0TimingOccasion. The coreset0Resources signal contains the frequency offset from the SSB to CORESET0 and the bandwidth of the CORESET0 resource grid. The coreset0TimingOccasion signal contains the slot offset from the even SFN frame head to the first monitored slot i.e. the slot within 2 system frames. The monitored slot timing offset subsystem converts the coreset0TimingOccasion slot offset to a timing reference count. The SSB pattern, SSB index, and SSB timing reference are used to compute the timing reference of the even SFN frame head, from which the timing reference value of CORESET0 is computed. A timing reference counter, synchronized with the SSB detection references, is used to track the SIB1 data stream. Once the start signal is asserted, the startController waits for the SIB1 timing reference to reach the target offset computed by the monitored slot timing offset subsystem and then triggers the OFDM demodulation to begin. The diagram shows an example of the timing references for the monitored SSB, the even frame head, and the CORESET0 timing occasion. These offsets depend on the configuration of the transmitting cell.

The grid demodulation algorithm also supports wideband grid demodulation beyond the SIB1 grid. The NR HDL Downlink Signal Measurements example shows how to use the wideband demodulation mode to perform signal quality measurements on the recevied resource grid.

NR HDL CORESET0 Decoding

This figure shows the nrhdlCORESET0Decoding model. The top level of the model reads the signals from the MATLAB base workspace, passes them to the CORESET0 Decoding subsystem, and writes the outputs back to the workspace.

CORESET0 Decoding Subsystem

The CORESET0 Decoding subsystem references the nrhdlCORESET0DecodingCore and nrhdlPolarDecodingChainCore models. The algorithm of the nrhdlCORESET0DecodingCore model is described in the next section. The nrhdlPolarDecodingChainCore model is covered in the NR HDL MIB Recovery example. The subsystem performs channel estimation and equalization, QPSK symbol demodulation, descrambling, rate recovery, polar decoding, and CRC decoding of CORESET0 candidates. The design provides back pressure with the nextFrame signal to indicate when it can accept a new candidate. The processing is split over two models to allow for the nrhdlPolarDecodingChainCore to be shared between the SSB decoding and SIB1 CORESET0 decoding in the NR HDL SIB1 Recovery example. This section describes the inputs and outputs for the subsystem.

Inputs

Outputs

Status Signal States

CORESET0 Decoding Model

This diagram shows the top level of the nrhdlCORESET0DecodingCore model. To decode CORESET0 a blind search is performed over multiple candidates. The correct candidate is determined by the CRC remainder equaling the SIB1 RNTI 65535. The design coordinates each search step and generates the required parameters to decode the candidate with the nrhdlPolarDecodingChainCore model. After a candidate is decoded, the CRC result is checked. If the CRC passes, the decoded data is output on the dciData port. If the CRC fails, the algorithm signals with nextFrame that it is ready for the next candidate. If all candidates are decoded with no success then searchFailed is set high. The number of search candidates per slot is determined from the searchSpaces input, this signal is a vector of 3 values corresponding to the number of candidates for the three possible aggregation values [4 8 16]. The design expects candidates to be input in decreasing order of aggregation level. The total number of searches is twice the search spaces since two slots are monitored for decoding. The firstOrSecondSlot output signals which slot the DCI was decoded in. The status signal can be used to monitor the progress of the decoding. Each candidate failure is indicated by state 4 and the final result is signalled by either state 5 (failure) or state 6 (success).

NR HDL SIB1 LDPC Decoding

This figure shows the nrhdlSIB1LPDCDecoding model. The top level of the model reads the signals from the MATLAB base workspace, passes them to the SIB1 LDPC Decoding subsystem, and writes the outputs back to the workspace.

SIB1 LDPC Decoding Subsystem

The SIB1 LDPC Decoding subsystem references the nrhdlLDPCDecodingChainCore model. The subsystem performs LDPC decoding, codeblock desegmentation, and CRC decoding. This section describes the inputs and outputs for the subsystem.

Inputs

Outputs

Status Signal States

SIB1 LDPC Decoding Model

This diagram shows the top level of the nrhdlLDPCDecodingChainCore model. The design accepts input LLRs along with a sample control bus and additional constants. The first stage performs LDPC rate recovery, this includes signal scaling and wordlength reduction to prepare the data for LDPC decoding. The second stage decodes the LDPC data using min-sum layered belief propagation with lifting factor from input port. For the SIB1 use case only base graph 2 is supported so the bgn input is constant. The algorithm then performs codeblock desegmentation. For SIB1 this only requires the removal of the padding bits from the end of the data to produce a length of tbs + 16 CRC bits. The final stage performs CRC decoding using CRC16 with no scrambling. The decoded SIB1 bits and the error status are output. Additionally, a status port is provided to show the algorithms progress. The output from the rate recovery stage is provided on the diagnostic port.

SIB1 Accelerators Simulation Setup

The diagram shows the simulation setup implemented by this example. 5G Toolbox functions are used to generate a test waveform. MATLAB reference code is then used to perform the steps required for MIB recovery - SSB search, demodulation, and decoding. The results provide the input data for the SIB1 demodulation stage. The same input is passed to both MATLAB and Simulink implementations of SIB1 demodulation, and the output grids are directly compared. The CORESET0 candidates are extracted from the grid and decoded using MATLAB and Simulink. The DCI result is used to extract the SIB1 LDPC codeword from the resource grid and the final decode is performed in MATLAB and Simulink. At each stage MATLAB and Simulink results are compared to confirm their equivalence.

The Test bench options section of the runNRSIB1AcceleratorModels script includes these variables to configure the simulation:

    Simulation Case    SSB Pattern    Subcarrier Spacing Common    PDCCH Config SIB1    SNR dB    Strongest SSB index    Lmax
    _______________    ___________    _________________________    _________________    ______    ___________________    ____

      "SimCase 1"       "Case C"                 30                       164             50               4              8  
      "SimCase 2"       "Case B"                 15                       100              6               3              4  
      "SimCase 3"       "Case A"                 30                         4             20               2              8  
      "SimCase 4"       "Case A"                 15                        84              7               0              4  

SIB1 Accelerators Simulation

Use the runNRSIB1AcceleratorModels script to run a SIB1 recovery simulation using the hardware accelerators. The script displays its progress at the MATLAB command prompt, and produces plots of inputs and outputs for analysis. This example shows the results of running "SimCase 1". The resource grids produced by MATLAB and Simulink from the SIB1 demodulation are displayed along with the difference between them and their relative mean squared error (MSE). The grid plots are labelled to highlight the decoded PDCCH and PDSCH. The DCI fields from CORESET0 decoding are displayed and the final SIB1 bits are compared. This comparison verifies that the Simulink implementations closely matches the MATLAB reference.

runNRSIB1AcceleratorModels;

Generating test waveform.
Searching for SSBs using MATLAB reference.
Demodulating the strongest SSB using MATLAB reference.
Decoding the demodulated SSB using MATLAB reference.
Demodulating the SIB1 grid using MATLAB reference.
Demodulating the SIB1 grid using Simulink model.
Running nrhdlSIB1Demodulation.slx
### Searching for referenced models in model 'nrhdlSIB1Demodulation'.
### Found 2 model reference targets to update.
### Starting serial model reference simulation build.
### Model reference simulation target for nrhdlDDCFR1Core is up to date.
### Model reference simulation target for nrhdlSIB1DemodulationFR1Core is up to date.

Build Summary

0 of 2 models built (2 models already up to date)
Build duration: 0h 0m 5.2346s
..........
MATLAB and Simulink grids relative MSE : -61.236 dB

Extracting CORESET0 candidates from the SIB1 grid.
Decoding CORESET0 candidates using MATLAB reference.
Decoding CORESET0 candidates using Simulink.
Running nrhdlCORESET0Decoding.slx
### Searching for referenced models in model 'nrhdlCORESET0Decoding'.
### Found 2 model reference targets to update.
### Starting serial model reference simulation build.
### Model reference simulation target for nrhdlCORESET0DecodingCore is up to date.
### Model reference simulation target for nrhdlPolarDecodingChainCore is up to date.

Build Summary

0 of 2 models built (2 models already up to date)
Build duration: 0h 0m 1.798s
..........
DCI from MATLAB:
                     RIV: 528
                TDDIndex: 0
    VRBToPRBInterleaving: 0
               ModCoding: 0
                      RV: 0
             SIIndicator: 0
                Reserved: 0

DCI from Simulink:
                     RIV: 528
                TDDIndex: 0
    VRBToPRBInterleaving: 0
               ModCoding: 0
                      RV: 0
             SIIndicator: 0
                Reserved: 0

DCI successfully decoded from Simulink grid with hardware acceleration

Extracting LDPC codeword from the SIB1 grid.
Decoding SIB1 using MATLAB reference.
Decoding SIB1 using Simulink.
Running nrhdlSIB1LDPCDecoding.slx
### Searching for referenced models in model 'nrhdlSIB1LDPCDecoding'.
### Found 1 model reference targets to update.
### Starting serial model reference simulation build.
### Model reference simulation target for nrhdlLDPCDecodingChainCore is up to date.

Build Summary

0 of 1 models built (1 models already up to date)
Build duration: 0h 0m 1.3849s
..........
SIB1 successfully decoded from Simulink grid with hardware acceleration
SIB1 bits from MATLAB and Simulink match

HDL Code Generation and Implementation Results

To generate the HDL code for this example, you must have an HDL Coder™ license. Use the makehdl and makehdltb commands to generate HDL code and an HDL test bench for the nrhdlSIB1Demodulation/SIB1 Demodulation, nrhdlCORESET0Decoding/CORESET0 Decoding or nrhdlSIB1LDPCDecoding/SIB1 LDPC Decoding subsystems. The resulting HDL code was synthesized for a Xilinx® Zynq®-7000 ZC706 evaluation board. The table shows the post place and route resource utilization results. The design meets timing with a clock frequency of 150 MHz.

Resource utilization for nrhdlSIB1Demodulation model:

       Resource        Usage
    _______________    _____

    Slice Registers    13018
    Slice LUTs          7711
    RAMB18                18
    RAMB36                10
    DSP48                 35

Resource utilization for nrhdlCORESET0Decoding model:

       Resource        Usage
    _______________    _____

    Slice Registers     8297
    Slice LUTs         11099
    RAMB18                 8
    RAMB36                 4
    DSP48                 16

Resource utilization for nrhdlSIB1LDPCDecoding model:

       Resource        Usage
    _______________    _____

    Slice Registers    61827
    Slice LUTs         42120
    RAMB18               289
    RAMB36                20
    DSP48                  3