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NR HDL Reference Applications Overview

Wireless HDL Toolbox™ contains several reference applications that implement and verify parts of a 5G NR downlink receiver. This page illustrates a workflow for designing and verifying complex algorithms for hardware, explains how the examples relate to each other, and shows which parts of the downlink receiver algorithm the examples cover.

For an introduction to the design and verification workflow used in these reference applications, see Introduction to 5G NR Signal Detection and Introduction to 5G NR Signal Detection using AMD RFSoC (SoC Blockset).

Family of Examples

The 5G Reference Applications page shows a family of examples that describe a workflow for designing and deploying an algorithm to hardware. Different examples describe different parts of the workflow. This diagram shows the complete workflow.

Each step in this workflow is demonstrated by one or more related examples.

  1. The MATLAB Golden Reference Algorithm step consists of the NR Cell Search and MIB and SIB1 Recovery (5G Toolbox) example, which shows the floating-point golden reference algorithm.

  2. The MATLAB Hardware Reference Algorithm step consists of the NR HDL Downlink Receiver MATLAB Reference example, which models hardware friendly algorithms and generates test waveforms. This MATLAB code covers cell search, MIB recovery, and SIB1 recovery, and bridges the gap between a mathematical algorithm and its hardware implementation. This code models the data flow and sample rate used in the hardware implementation, operates on vectors and matrices of floating-point data samples, and does not support HDL code generation. For the success rate of the hardware reference algorithm, see NR HDL Receiver Performance.

  3. The Simulink Fixed-Point Implementation Model step consists of multiple examples that cover sections of the downlink receiver chain. These models operate on fixed-point data and are optimized for HDL code generation. The algorithms in these models are verified against the golden and reference design scripts, and have been tested on boards to ensure that they decode over-the-air waveforms. They are ready for integration into your own designs and deploying to boards.

    • The NR HDL Cell Search example demonstrates a 5G cell search Simulink® subsystem that uses the same algorithm as the MATLAB® reference.

    • The NR HDL MIB Recovery example builds on the cell search example and adds a broadcast channel decoding and MIB recovery subsystem.

    • The Hardware Accelerators for NR SIB1 Recovery example shows the SIB1 grid recovery, CORESET0 decoding, and LDPC decoding sections of the SIB1 recovery algorithm implemented for hardware.

    • The NR HDL SIB1 Recovery example builds on the MIB recovery example and integrates the SIB1 hardware accelerators to form a complete SIB1 recovery system.

    • The NR HDL SIB1 Recovery for FR2 example shows cell search, MIB, and SIB1 recovery models that are extended to support FR2.

    The block diagram shows the 5G NR downlink receiver algorithm as implemented for hardware.

    The algorithm detects, demodulates, and decodes 5G NR synchronization signal blocks (SSBs) and recovers SIB1. It is a hardware-friendly version of the corresponding steps in the NR Cell Search and MIB and SIB1 Recovery (5G Toolbox) example. At the top level, the algorithm consists of a search controller, an SSB detector, an SSB decoder, SIB1 grid demodulator, and SIB1 decoder. The SIB1 decoder includes PDCCH and PDSCH decoder algorithms that use hardware polar decoder and LDPC decoder blocks. The shaded areas show which examples implement which parts of the downlink receiver.

  4. The Simulink SoC Deployment Model step consists of the Deploy NR HDL Reference Applications on FPGAs and SoCs examples, which build on the fixed-point implementation models and use hardware support packages to deploy the algorithms on hardware. For the success rate of the algorithm running on hardware, see NR HDL Receiver Performance.

For a general description of how MATLAB and Simulink can be used together to develop deployable models, see Wireless Communications Design for ASICs, FPGAs, and SoCs.

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