Turnkey workflows are deprecated https://www.mathworks.com/products/hdl-coder.html
To target FPGA and SoC devices, use the IP core generation workflow. For more information, see Targeting FPGA & SoC Hardware.
Both IP Core Generation and (prior to R2022a) FPGA Turnkey workflows allowed taking MATLAB/Simulink/Stateflow/Simscape algorithms onto FPGA/SoC boards.
However IP Core Generation workflow is superior and adopts the IP-centric design methodology. You can generate your own custom HDL IP core from your Simulink/MATLAB algorithm. This custom IP core is sharable and reusable, and also comes with a generated IP core report.
You can then integrate the generated IP core from this workflow into a larger design in FPGA design tools such as Altera Qsys, or AMD/Xilinx Vivado/IP Integrator. You can also register your Vivado/Qsys project as a custom reference design, so that the IP Core Generation workflow can help you integrate the IP core into the reference design automatically.
The previous FPGA Turnkey workflow had very limited features, does not use the IP-centric design methodology. Instead, it generates the HDL codes\ for the whole FPGA design, including the algorithm HDL code, the FPGA top level wrapper HDL code, and FPGA Pin mapping constraints, so that you can run your algorithm on standard alone FPGA board. The FPGA Turnkey workflow supported very limited FPGA boards, and did not support advanced AMD SoCs such as Zynq or Versal or other FPGA families such as Altera.
We recommend you upgrade to R2024a release of HDL Coder and transition to the IP core generation and Custom Reference Design workflows to target the FPGA/SoC boards.
