Hello Cheri,
If you're generating HDL code from a Simulink subsystem using makehdl, the behavior you're describing is already supported. When you use a vector signal of size [4x1] or [1x4], where each element is a 16-bit fixed-point or integer type, HDL Coder interprets this as a vector of four elements. In the generated VHDL code, this would typically appear as a structure like vector_of_std_logic_vector16(0 TO 3), as shown in the example below:
However, if you're using the IP core generation workflow, the behavior depends on how the ports are mapped. For instance, when a vector port is mapped to an "External Port", HDL Coder flattens the vector into a single std_logic_vector, resulting in a 64-bit wide port (i.e., std_logic_vector(63 downto 0)). This is currenlty expected behavior for external interfaces.
If this doesn't align with what you're seeing or trying to achieve, could you clarify which workflow you're using (e.g., makehdl vs. IP Core Generation workflow)? And if you're using the IP core generation workflow, how are you configuring the interface (e.g., External Port, AXI4)? Additionally, it would be helpful to understand why you're aiming to preserve the vector structure at the boundary and why the makehdl approach does not meet your requirements.
Best,
Angela
