what is the difference between FPGA Turnkey and IP Core Generation?

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Yashar
Yashar 2015-8-7
编辑： Kiran Kintali 2024-1-29
In HDL Workflow advisor one could choose between different target workflows such as Generic ASICS/FPGA, FPGA Turnkey, IP Core Generation, FPGA-in-the-loop, Simulink real-time FPGA I/O. I have researched for almost half a day and I couldn't find a clear explanation of differences between these modes. In particular, I would like to know about difference between FPGA Turnkey and IP Core Generation. It is highly appreciated if someone briefly explain this, or cite references where this topic is discussed.
Best regards, Yashar

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Wang Chen
Wang Chen 2015-8-7
编辑：Wang Chen 2015-8-7
Hi Yashar,
Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/SoC boards.
IP Core Generation workflow adopts the IP-centric design methodology. You can generate your own custom HDL IP core from your Simulink/MATLAB algorithm. This custom IP core is sharable and reusable, and also comes with a generated IP core report.
http://www.mathworks.com/help/releases/R2015a/hdlcoder/ug/custom-ip-core-generation.html
http://www.mathworks.com/discovery/ip-core-generation.html?s_tid=srchtitle
You can then integrate the generated IP core into a larger design in FPGA design tools such as Altera Qsys, or Xilinx Vivado/IP Integrator. You can also register your Vivado/Qsys project as a custom reference design, so the IP Core Generation workflow can help you integrate the IP core into the reference design automatically.
http://www.mathworks.com/help/releases/R2015a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-soc-workflow.html
FPGA Turnkey workflow does not use the IP-centric design methodology. Instead, it generates the HDL codes for the whole FPGA design, including the algorithm HDL code, the FPGA top level wrapper HDL code, and FPGA Pin mapping constraints, so you can run your algorithm on standard alone FPGA board. FPGA Turnkey workflow targets FPGA boards only, it does not support Zynq/Altera SoC boards
http://www.mathworks.com/help/releases/R2015a/hdlcoder/xilinx-fpga-boards.html
Thanks, Wang
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冰昊
冰昊 2024-1-27
@Wang Chen
For this question, I want to know more.
what is the difference between FPGA-in-the-loop, Simulink real-time FPGA I/O？
And, what is the difference between Generic ASICS/FPGA and IP Core Generation.
Thanks.
Kiran Kintali
Kiran Kintali 2024-1-28
编辑：Kiran Kintali 2024-1-29
HDL Coder Workflows:
  • Generic ASIC/FPGA Workflow: Generate Synthesizable RTL (VHDL, Verilog, SystemVerilog)
  • IP Core Generation: Wrap the Generated RTL with custom AXI and other industry standard interfaces, automatically integrate the generated IP core into a bigger reference design system, and optionally generate SW interface to the IP core for HW/SW co-design. See notes here Generate IP Core and Bitstream
  • Simulink RT FPGA IO: Real Time hardware targeting using Speedgoat
  • FPGA IO: Run and verify the HDL Coder generated bitstream from your IP core design on your choice target hardware. Free running FPGA workflow. Send and receive data from MATLAB to target hardware.
  • FPGA-in-the-loop: Simulink runs in lockstep with the supported FPGA board (requires HDL Verifier) for hardware debugging in conjunction with Simulink.
  • FPGA-turnkey: Stand-alone FPGA only (no SoC support) workflow. Now deprecated. Recommend to use the more advanced IP Core and SoC targeting workflows shown above.

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Kiran Kintali
Kiran Kintali 2024-1-28
Targeting FPGA & SoC Hardware with HDL Coder Workflow
Design a system that you can deploy on hardware or a combination of hardware and software. Deploy your MATLAB® or Simulink® design:
  • As hardware and software on system-on-chip (SoC) platforms, such as Xilinx® Zynq®, Intel® SoC or Microchip SoC.
  • On standalone FPGA boards, such as an Intel FPGA or a Xilinx FPGA board.
  • On platforms that have a separate FPGA and processor, such as the Simulink Real-Time™ target machine with FPGA I/O boards.
If you are using an SoC platform or a platform that has a separate FPGA and processor, you can partition your design to generate hardware that targets the FPGA fabric and software that runs on the embedded processor of the target platform.

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