Attached model has several Sample and Hold Blocks in addition to Sin function configured to use CORDIC architecture.
The flatten hierarchy option works as expected during HDL Code generation.
>> hdlsaveparams('simplifiedModel_SH_21a/DUT')
%% Set Model 'simplifiedModel_SH_21a' HDL parameters
hdlset_param('simplifiedModel_SH_21a', 'HDLSubsystem', 'simplifiedModel_SH_21a');
% Set SubSystem HDL parameters
hdlset_param('simplifiedModel_SH_21a/DUT', 'FlattenHierarchy', 'on');
>>
>> makehdl('simplifiedModel_SH_21a/DUT')
### Generating HDL for 'simplifiedModel_SH_21a/DUT'.
### Using the config set for model simplifiedModel_SH_21a for HDL code generation parameters.
### Running HDL checks on the model 'simplifiedModel_SH_21a'.
### Begin compilation of the model 'simplifiedModel_SH_21a'...
### Applying HDL optimizations on the model 'simplifiedModel_SH_21a'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 12 cycles.
### Output port 2: 12 cycles.
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'simplifiedModel_SH_21a'.
### Working on simplifiedModel_SH_21a/DUT/Sin as hdlsrc\simplifiedModel_SH_21a\Sin.vhd.
### Working on simplifiedModel_SH_21a/DUT as hdlsrc\simplifiedModel_SH_21a\DUT.vhd.
### Generating package file hdlsrc\simplifiedModel_SH_21a\DUT_pkg.vhd.
### Code Generation for 'simplifiedModel_SH_21a' completed.
### Creating HDL Code Generation Check Report DUT_report.html
### HDL check for 'simplifiedModel_SH_21a' complete with 0 errors, 0 warnings, and 1 messages.
### HDL code generation complete.
>>
.
>> find_system('simplifiedModel_SH_21a/DUT')
ans =
26×1 cell array
{'simplifiedModel_SH_21a/DUT' }
{'simplifiedModel_SH_21a/DUT/IN1' }
{'simplifiedModel_SH_21a/DUT/IN2' }
{'simplifiedModel_SH_21a/DUT/IN3' }
{'simplifiedModel_SH_21a/DUT/IN4' }
{'simplifiedModel_SH_21a/DUT/Data Type Conversion'}
{'simplifiedModel_SH_21a/DUT/SS1' }
{'simplifiedModel_SH_21a/DUT/SS1/IN2' }
{'simplifiedModel_SH_21a/DUT/SS1/IN1' }
{'simplifiedModel_SH_21a/DUT/SS1/SH2' } % SAMPLE and HOLD
{'simplifiedModel_SH_21a/DUT/SS1/TSS1' }
{'simplifiedModel_SH_21a/DUT/SS1/TSS1/input' }
{'simplifiedModel_SH_21a/DUT/SS1/TSS1/Trigger' }
{'simplifiedModel_SH_21a/DUT/SS1/TSS1/output' }
{'simplifiedModel_SH_21a/DUT/SS1/Unit Delay2' }
{'simplifiedModel_SH_21a/DUT/SS1/Unit Delay3' }
{'simplifiedModel_SH_21a/DUT/SS1/OUT1' }
{'simplifiedModel_SH_21a/DUT/SS2' }
{'simplifiedModel_SH_21a/DUT/SS2/In1' }
{'simplifiedModel_SH_21a/DUT/SS2/In2' }
{'simplifiedModel_SH_21a/DUT/SS2/SH1' } % SAMPLE and HOLD
{'simplifiedModel_SH_21a/DUT/SS2/Unit Delay2' }
{'simplifiedModel_SH_21a/DUT/SS2/Out1' }
{'simplifiedModel_SH_21a/DUT/Sin' } % SIN (CORDIC)
{'simplifiedModel_SH_21a/DUT/OUT1' }
{'simplifiedModel_SH_21a/DUT/OUT2' }
>>
