Using Reference Model for HDL code Generation

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Hi,
Is there anyway to generate HDL code for a reference model . For example, let's say I have a subsystem that I would like to use across my design. There are currently two problems with repeating the same subsystem across the model. One is that the generated code outputs different Verilog files for each of the called subsystem. Second is that if I want to make a change to the subsystem, the change will not happen across the other subsystems. Is there a way to create a subsystem, that can be modified globally and at the same time generate only one Verilog file?
Many thanks, Kamyar

采纳的回答

Kiran Kintali
Kiran Kintali 2018-4-10
Yes, you can use model reference block with HDLCoder to generate HDL code without creating duplicate copies.
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Kamyar Khosravi
Kamyar Khosravi 2018-4-11
Thank you for the feedback I managed to do it successfully.

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更多回答(1 个)

Tim McBrayer
Tim McBrayer 2018-4-10
Mark each instance of the subsystem as atomic. When marked atomic, it will generate only one output file for all instances.
Secondly, you can place your subsystem in a library. When you use a library block, each copy refers back to the original library block. Changing the library block will cause every instance to have the same change.
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Kamyar Khosravi
Kamyar Khosravi 2018-4-11
Thank you for the feedback I managed to do it successfully. Creating a library is indeed very interesting feature. Thank you for the response

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