HDL Coder supports a single entry point called DUT from which VHDL/Verilog is generated.
Consider making one top level dut.m file with the following interface and use it for HDL code generation.
function [y1, y2] = dut(u1, u2)
y1 = call_to_module1(u1);
y2 = call_to_module2(u2);
end