can a single model containing 2 different subsystems generate HDL and C code for the subsystems seperately?
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I am trying to simulate a model containing FPGA and ADSP as 2 different subsystems. Can i generate HDL code for FPGA subsystem and C code for ADSP subsystem from a single model?
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Kiran Kintali
2019-11-15
Yes. You can generate code independently using embedded Coder and HDL Coder products for the two subsystems and integrate the code manually.
You can also use the shipping HW/SW codesign workflow advisor to automate some of the steps and avoid manual integration. Check out this HDLCoder product example for one such application.
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