The root cause of the issue are the commented-through blocks in the DUT model. If you right-click on the DUT block and select HDL Code -> Check Subsystem Compatibility, the HDL Code Generation Check report indicates that 5 blocks are commented-through, which is apparently not supported by HDL Coder. For example check this report error:
The 'sim_05092019_1100/DUT1/cross_correlator (RAM short)/LTE/slice/abs^2' block is commented through. HDL code generation is not supported for blocks that are commented through.
If you remove these blocks and replace them with a connecting line, Task 1.2 completes successfully. I would suggest that you try this (best to make a backup copy of the model), then proceeds through the remainder of the HDL Workflow Advisor.
The above conclusions are the result of running the HDL Model Checker;
web(fullfile(docroot, 'hdlcoder/hdl-model-checker.html'))
Specifically this check:
web(fullfile(docroot, 'hdlcoder/ug/check-for-ports-and-subsystems.html'))
Please follow the below link to search for the required information regarding the current release:
