Welcome to the HDL Coder Video Series. In this video series we will learn a popular production proven path to take a MATLAB digital signal processing algorithm through Simulink, Fixed-Point Designer, and HDL Coder to target an FPGA.
In the first part of the video series we will discuss the strength of MATLAB and Simulink and provide an overview of the HDL Coder Self-Guided Tutorial available on the MathWorks File Exchange website.
HDL Coder generates synthesizable VHDL or Verilog from MATLAB functions, Simulink models, and Stateflow charts that can be used to target FPGA or ASIC hardware.
MATLAB is a high-level language and interactive environment where complex mathematical operations can be easily performed on large sets of data. This ability of MATLAB makes it an ideal tool to develop digital signal-processing algorithms. To target such a powerful language onto hardware, we need to understand that the FPGA hardware is a fixed set of resource. The FPGA hardware has limited bandwidth of resources consisting of input/output blocks, memory, and DSP slices which must be effectively used to achieve an optimized design architecture while achieving the desired outcome. As resources are fixed in hardware, to perform operations on large data sets we will work on stream of bits while coordinating the timing to obtain the right answer.
Simulink provides an environment where you can describe how the algorithm design will work with the stream of data and simulate before moving to hardware implementation. Simulink has a built-in sense of time and aids in visualizing the data types and sizes, propagation through operations which are key to creating a good hardware architecture. Simulink has an HDL-optimized library with more than 250 blocks and compatible with HDL Code Generation.
Thus, to deploy MATLAB algorithm on a FPGA, the recommended workflow is to use MATLAB and Simulink together to combine textual and graphical programming in a simulation environment. We will use the MATLAB algorithm as a golden reference, describe the hardware architecture in Simulink, convert to fixed point, and utilize Simulink’s visualization to optimize the generated HDL code. Thus, each step in Simulink can be verified in MATLAB and utilizes MATLAB as a test and visualization environment.
To illustrate the workflow, we will utilize the HDL Coder Self-Guided Tutorial example from MathWorks File Exchange website.
The tutorial comes with a visual guide and provides step-by-step instructions to implement a MATLAB algorithm onto a FPGA. In addition, the tutorial provides the necessary MATLAB and test bench scripts.
In the MATLAB Reference Script, the pulse to detect is created and is inserted in a transmit signal. Noise is added to represent a real world receive signal. To detect the pulse in MATLAB we will utilize the entire “frame” of the received signal and pass it through a matched filter with desired coefficients. This algorithm will be our MATLAB golden reference, which will detect the peak value and its location.
Hardware works on a continuous stream of bits, and peak detection is obtained by sliding a window over a sample of the bit-stream. To ensure this method gives us the desired result, we create a MATLAB algorithm which represents the hardware implementation. This we will call the hardware-friendly algorithm.
The hardware implementation algorithm detects the peak within a sliding window of the last 11 samples under the criteria. The middle sample is the largest and the middle sample is greater than a pre-determined threshold. This algorithm will be utilized to verify and compare the output of the Simulink model implementation.
In the first part of this video series on the HDL Coder, we have discussed the strengths of MATLAB and Simulink environment and provided an overview of the Pulse Detector MATLAB algorithm, which will be used to highlight the HDL Coder Workflow required to implement a MATLAB algorithm on a FPGA.
In the next video we will design the Simulink implementation of the Pulse Detector Algorithm and compare it to the MATLAB golden reference.
