Hardware design often begins with system and algorithm design in Simulink® and MATLAB®, followed by manually writing a detailed hardware description language (HDL) representation that is used to implement FPGA or ASIC hardware.
Manually writing low-level HDL limits how broadly the hardware design team can explore different architectures, increases the amount of bugs introduced, and limits the ability to reuse the algorithm for other projects.
HDL Coder™ automatically generates synthesizable Verilog or VHDL code from Simulink and MATLAB for implementing hardware designs. In this approach, system algorithm and hardware design engineers can collaborate to explore a broader solution space and eliminate the error-prone task of manually writing HDL. As a result, new applications gain the performance and power consumption benefits of implementing algorithms in digital hardware. In addition, automatic HDL code generation from a high-level model makes it much easier to reuse code for other projects.
See below for a typical workflow displaying algorithm to hardware design.
For additional information, see HDL Coder.