ASIC Testbench is an add-on to HDL Verifier™ that automatically generates verification components from MATLAB® code and Simulink® models for use in ASIC and FPGA production environments. By generating verification components and environments automatically, ASIC and FPGA project teams can reuse MATLAB or Simulink testbenches to build RTL testbenches more quickly and shorten verification project timelines.
ASIC Testbench works with MathWorks® coders to generate C code, with wrappers using the SystemVerilog Direct Programming Interface, or DPI. The source model can be either MATLAB code or a Simulink model. These generated DPI models run natively in HDL simulators including Siemens® Questa™, Cadence® Xcelium™, Synopsys® VCS®, and Vivado® simulator from AMD®.
ASIC Testbench can generate verification components for the Universal Verification Methodology from MATLAB code or Simulink models. Teams can generate UVM top models with testbenches and behavioral designs under test (DUTs) or generate individual UVM components to incorporate into existing UVM environments.
Teams can extend testbenches to refine your verification using protocol-specific drivers, constrained random sequences, and parameterized scoreboards. With Simulink models, internal signals can be made observable in the generated testbench by specifying test points and generating access functions for checkers and scoreboards.
ASIC and FPGA project teams can generate native SystemVerilog assertions using the Assertion block in a Simulink model, giving the same assertion behavior in both Simulink and in RTL verification environments.
ASIC Testbench can also build SystemC™ virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations.
ASIC Testbench can be installed from the Add-On Explorer starting with release 2023b.
